BUS CONTROL SYSTEM FOR DATA PROCESSOR

PURPOSE:To sufficiently display the performance of an access part by connecting gate circuits among plural access parts through an address bus and a data bus and an accessed part so as to correspond to the plural access parts. CONSTITUTION:Plural gate circuits 50 and 53 are connected among the plural access parts 10, 11 connected through the address bus 40 and the data bus 41 and the accessed part 20 so as to correspond to the access parts 10, 11. In the constitution, address enable signals are applied from a bus controller 30 to respective gates 50 to 53 through respective gate lines. The reading clock of each of the access parts 10, 11 is divided into four clocks and the contents of a RAM 20 are alternately read out. Although each of the access parts 10, 11 sends addresses corresponding to four clock and inputs data at the 4th clock, the RAM 20 outputs data at the 1st clock. Thereby, the output timing of the addresses is made different from the input timing of data and the effective period of each address becomes 1.5 clocks. Consequently, respective access parts 10, 11 can sufficiently display their performance.