MODE SWITCHING CIRCUIT FOR DATA PROCESSING

PURPOSE:To curtail the power consumption without operating a data processing circuit which is not selected by controlling a clock inputted to the data processing circuit by using a selecting signal, and supplying the clock to only the selected data processing circuit. CONSTITUTION:Data inputted from...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHIMAMORI TETSUYA, IMAI MASAMICHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHIMAMORI TETSUYA
IMAI MASAMICHI
description PURPOSE:To curtail the power consumption without operating a data processing circuit which is not selected by controlling a clock inputted to the data processing circuit by using a selecting signal, and supplying the clock to only the selected data processing circuit. CONSTITUTION:Data inputted from a data input terminal 11 is supplied simulta neously to a first data processing circuit and a second data processing circuit 2. A first data processing circuit 1 and a second data processing circuit 2 input data and a clock, execute a data processing, and output signals S1,S2, respective ly. A selecting circuit 3 inputs a first data processing circuit output signal S1, a second data processing circuit output signal S2, and a selecting signal from a selecting signal input terminal 13, and outputs a selecting circuit output signal S3. In such a state, the clock is supplied to only the data processing circuit selected by the selecting circuit 3, and the data processing circuit which is not selected by the selecting circuit 3 does not operate since the clock is not supplied. In such a way, the power consumptiom can be curtailed.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04123116A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04123116A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04123116A3</originalsourceid><addsrcrecordid>eNrjZNDy9XdxVQgO9wxx9vD0c1dw9gxyDvUMUXDzD1JwcQxxVAgI8nd2DQ4GyvEwsKYl5hSn8kJpbgZFN1egNt3Ugvz41OKCxOTUvNSSeK8ADwMTQyNjQ0MzR2Ni1AAAT7QkvQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MODE SWITCHING CIRCUIT FOR DATA PROCESSING</title><source>esp@cenet</source><creator>SHIMAMORI TETSUYA ; IMAI MASAMICHI</creator><creatorcontrib>SHIMAMORI TETSUYA ; IMAI MASAMICHI</creatorcontrib><description>PURPOSE:To curtail the power consumption without operating a data processing circuit which is not selected by controlling a clock inputted to the data processing circuit by using a selecting signal, and supplying the clock to only the selected data processing circuit. CONSTITUTION:Data inputted from a data input terminal 11 is supplied simulta neously to a first data processing circuit and a second data processing circuit 2. A first data processing circuit 1 and a second data processing circuit 2 input data and a clock, execute a data processing, and output signals S1,S2, respective ly. A selecting circuit 3 inputs a first data processing circuit output signal S1, a second data processing circuit output signal S2, and a selecting signal from a selecting signal input terminal 13, and outputs a selecting circuit output signal S3. In such a state, the clock is supplied to only the data processing circuit selected by the selecting circuit 3, and the data processing circuit which is not selected by the selecting circuit 3 does not operate since the clock is not supplied. In such a way, the power consumptiom can be curtailed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920423&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04123116A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920423&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04123116A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIMAMORI TETSUYA</creatorcontrib><creatorcontrib>IMAI MASAMICHI</creatorcontrib><title>MODE SWITCHING CIRCUIT FOR DATA PROCESSING</title><description>PURPOSE:To curtail the power consumption without operating a data processing circuit which is not selected by controlling a clock inputted to the data processing circuit by using a selecting signal, and supplying the clock to only the selected data processing circuit. CONSTITUTION:Data inputted from a data input terminal 11 is supplied simulta neously to a first data processing circuit and a second data processing circuit 2. A first data processing circuit 1 and a second data processing circuit 2 input data and a clock, execute a data processing, and output signals S1,S2, respective ly. A selecting circuit 3 inputs a first data processing circuit output signal S1, a second data processing circuit output signal S2, and a selecting signal from a selecting signal input terminal 13, and outputs a selecting circuit output signal S3. In such a state, the clock is supplied to only the data processing circuit selected by the selecting circuit 3, and the data processing circuit which is not selected by the selecting circuit 3 does not operate since the clock is not supplied. In such a way, the power consumptiom can be curtailed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDy9XdxVQgO9wxx9vD0c1dw9gxyDvUMUXDzD1JwcQxxVAgI8nd2DQ4GyvEwsKYl5hSn8kJpbgZFN1egNt3Ugvz41OKCxOTUvNSSeK8ADwMTQyNjQ0MzR2Ni1AAAT7QkvQ</recordid><startdate>19920423</startdate><enddate>19920423</enddate><creator>SHIMAMORI TETSUYA</creator><creator>IMAI MASAMICHI</creator><scope>EVB</scope></search><sort><creationdate>19920423</creationdate><title>MODE SWITCHING CIRCUIT FOR DATA PROCESSING</title><author>SHIMAMORI TETSUYA ; IMAI MASAMICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04123116A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIMAMORI TETSUYA</creatorcontrib><creatorcontrib>IMAI MASAMICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIMAMORI TETSUYA</au><au>IMAI MASAMICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MODE SWITCHING CIRCUIT FOR DATA PROCESSING</title><date>1992-04-23</date><risdate>1992</risdate><abstract>PURPOSE:To curtail the power consumption without operating a data processing circuit which is not selected by controlling a clock inputted to the data processing circuit by using a selecting signal, and supplying the clock to only the selected data processing circuit. CONSTITUTION:Data inputted from a data input terminal 11 is supplied simulta neously to a first data processing circuit and a second data processing circuit 2. A first data processing circuit 1 and a second data processing circuit 2 input data and a clock, execute a data processing, and output signals S1,S2, respective ly. A selecting circuit 3 inputs a first data processing circuit output signal S1, a second data processing circuit output signal S2, and a selecting signal from a selecting signal input terminal 13, and outputs a selecting circuit output signal S3. In such a state, the clock is supplied to only the data processing circuit selected by the selecting circuit 3, and the data processing circuit which is not selected by the selecting circuit 3 does not operate since the clock is not supplied. In such a way, the power consumptiom can be curtailed.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH04123116A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title MODE SWITCHING CIRCUIT FOR DATA PROCESSING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T00%3A33%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHIMAMORI%20TETSUYA&rft.date=1992-04-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH04123116A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true