MANUFACTURE OF MULTILAYER WIRING BOARD

MANUFACTURE OF MULTILAYER WIRING BOARD

PURPOSE:To eliminate the partial disconnection of a viahole of small diameter by a method wherein etching is carried out before a plating resist is removed. CONSTITUTION:A plating resist 1 whose pattern is opposite to that of a circuit is formed on a conductor 3 of a substrate provided with a plated...

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1. Verfasser: TADOKORO FUJIO
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CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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creator TADOKORO FUJIO
description PURPOSE:To eliminate the partial disconnection of a viahole of small diameter by a method wherein etching is carried out before a plating resist is removed. CONSTITUTION:A plating resist 1 whose pattern is opposite to that of a circuit is formed on a conductor 3 of a substrate provided with a plated through-hole. A plating 2 such as a solder plating is deposited on the circuit and the through- hole, etching is executed, and the plating resist 1 is separated. A circuit is formed through etching. As an etching process is carried out as a pre-treatment, a bitten part 5 is provided to the conductor 3 in the pre-treatment to partially disconnect it, and when the circuit is formed after the resist is removed, the partially disconnected bitten part 5 can be formed into a fully disconnected part 6 within a prescribed etching process time.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH0382191A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH0382191A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH0382191A3</originalsourceid><addsrcrecordid>eNrjZFDzdfQLdXN0DgkNclXwd1PwDfUJ8fRxjHQNUgj3DPL0c1dw8ncMcuFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GxhZGhpaGjsZEKAEAjpUjbQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURE OF MULTILAYER WIRING BOARD</title><source>esp@cenet</source><creator>TADOKORO FUJIO</creator><creatorcontrib>TADOKORO FUJIO</creatorcontrib><description>PURPOSE:To eliminate the partial disconnection of a viahole of small diameter by a method wherein etching is carried out before a plating resist is removed. CONSTITUTION:A plating resist 1 whose pattern is opposite to that of a circuit is formed on a conductor 3 of a substrate provided with a plated through-hole. A plating 2 such as a solder plating is deposited on the circuit and the through- hole, etching is executed, and the plating resist 1 is separated. A circuit is formed through etching. As an etching process is carried out as a pre-treatment, a bitten part 5 is provided to the conductor 3 in the pre-treatment to partially disconnect it, and when the circuit is formed after the resist is removed, the partially disconnected bitten part 5 can be formed into a fully disconnected part 6 within a prescribed etching process time.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19910408&amp;DB=EPODOC&amp;CC=JP&amp;NR=H0382191A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19910408&amp;DB=EPODOC&amp;CC=JP&amp;NR=H0382191A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TADOKORO FUJIO</creatorcontrib><title>MANUFACTURE OF MULTILAYER WIRING BOARD</title><description>PURPOSE:To eliminate the partial disconnection of a viahole of small diameter by a method wherein etching is carried out before a plating resist is removed. CONSTITUTION:A plating resist 1 whose pattern is opposite to that of a circuit is formed on a conductor 3 of a substrate provided with a plated through-hole. A plating 2 such as a solder plating is deposited on the circuit and the through- hole, etching is executed, and the plating resist 1 is separated. A circuit is formed through etching. As an etching process is carried out as a pre-treatment, a bitten part 5 is provided to the conductor 3 in the pre-treatment to partially disconnect it, and when the circuit is formed after the resist is removed, the partially disconnected bitten part 5 can be formed into a fully disconnected part 6 within a prescribed etching process time.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1991</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDzdfQLdXN0DgkNclXwd1PwDfUJ8fRxjHQNUgj3DPL0c1dw8ncMcuFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GxhZGhpaGjsZEKAEAjpUjbQ</recordid><startdate>19910408</startdate><enddate>19910408</enddate><creator>TADOKORO FUJIO</creator><scope>EVB</scope></search><sort><creationdate>19910408</creationdate><title>MANUFACTURE OF MULTILAYER WIRING BOARD</title><author>TADOKORO FUJIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0382191A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1991</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>TADOKORO FUJIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TADOKORO FUJIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURE OF MULTILAYER WIRING BOARD</title><date>1991-04-08</date><risdate>1991</risdate><abstract>PURPOSE:To eliminate the partial disconnection of a viahole of small diameter by a method wherein etching is carried out before a plating resist is removed. CONSTITUTION:A plating resist 1 whose pattern is opposite to that of a circuit is formed on a conductor 3 of a substrate provided with a plated through-hole. A plating 2 such as a solder plating is deposited on the circuit and the through- hole, etching is executed, and the plating resist 1 is separated. A circuit is formed through etching. As an etching process is carried out as a pre-treatment, a bitten part 5 is provided to the conductor 3 in the pre-treatment to partially disconnect it, and when the circuit is formed after the resist is removed, the partially disconnected bitten part 5 can be formed into a fully disconnected part 6 within a prescribed etching process time.</abstract><oa>free_for_read</oa></addata></record>
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subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title MANUFACTURE OF MULTILAYER WIRING BOARD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T19%3A24%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TADOKORO%20FUJIO&rft.date=1991-04-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH0382191A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true