INFORMATION PROCESSOR
PURPOSE:To evaluate a cache coincidence processing unit without putting other processor except its processor in actual operation by performing cache coincidence processing for the cache memory of the processor when the processor rewrites data on its main storage device. CONSTITUTION:When the value o...
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| creator | OI EIJI |
| description | PURPOSE:To evaluate a cache coincidence processing unit without putting other processor except its processor in actual operation by performing cache coincidence processing for the cache memory of the processor when the processor rewrites data on its main storage device. CONSTITUTION:When the value of a flip-flop 10 is '1', namely, when the comparison result of a processor number is made forcibly dissident, processing for an address array 23 is carried out with a cache coincidence processing request signal 103 from a system controller 2 and a stored address 104 irrelevantly to the comparison result of a comparator 12. Therefore, the cache coincidence processing is carried out similarly to a case wherein a processor number 105 from the system controller 2 indicates the processor number of another device. Consequently, the cache coincidence processing unit can be evaluated without putting other processors except this device in actual operation. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH0352043A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH0352043A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH0352043A3</originalsourceid><addsrcrecordid>eNrjZBD19HPzD_J1DPH091MICPJ3dg0O9g_iYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgEeBsamRgYmxo7GRCgBAHqbHuQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INFORMATION PROCESSOR</title><source>esp@cenet</source><creator>OI EIJI</creator><creatorcontrib>OI EIJI</creatorcontrib><description>PURPOSE:To evaluate a cache coincidence processing unit without putting other processor except its processor in actual operation by performing cache coincidence processing for the cache memory of the processor when the processor rewrites data on its main storage device. CONSTITUTION:When the value of a flip-flop 10 is '1', namely, when the comparison result of a processor number is made forcibly dissident, processing for an address array 23 is carried out with a cache coincidence processing request signal 103 from a system controller 2 and a stored address 104 irrelevantly to the comparison result of a comparator 12. Therefore, the cache coincidence processing is carried out similarly to a case wherein a processor number 105 from the system controller 2 indicates the processor number of another device. Consequently, the cache coincidence processing unit can be evaluated without putting other processors except this device in actual operation.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19910306&DB=EPODOC&CC=JP&NR=H0352043A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19910306&DB=EPODOC&CC=JP&NR=H0352043A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OI EIJI</creatorcontrib><title>INFORMATION PROCESSOR</title><description>PURPOSE:To evaluate a cache coincidence processing unit without putting other processor except its processor in actual operation by performing cache coincidence processing for the cache memory of the processor when the processor rewrites data on its main storage device. CONSTITUTION:When the value of a flip-flop 10 is '1', namely, when the comparison result of a processor number is made forcibly dissident, processing for an address array 23 is carried out with a cache coincidence processing request signal 103 from a system controller 2 and a stored address 104 irrelevantly to the comparison result of a comparator 12. Therefore, the cache coincidence processing is carried out similarly to a case wherein a processor number 105 from the system controller 2 indicates the processor number of another device. Consequently, the cache coincidence processing unit can be evaluated without putting other processors except this device in actual operation.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1991</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBD19HPzD_J1DPH091MICPJ3dg0O9g_iYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgEeBsamRgYmxo7GRCgBAHqbHuQ</recordid><startdate>19910306</startdate><enddate>19910306</enddate><creator>OI EIJI</creator><scope>EVB</scope></search><sort><creationdate>19910306</creationdate><title>INFORMATION PROCESSOR</title><author>OI EIJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0352043A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1991</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OI EIJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OI EIJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INFORMATION PROCESSOR</title><date>1991-03-06</date><risdate>1991</risdate><abstract>PURPOSE:To evaluate a cache coincidence processing unit without putting other processor except its processor in actual operation by performing cache coincidence processing for the cache memory of the processor when the processor rewrites data on its main storage device. CONSTITUTION:When the value of a flip-flop 10 is '1', namely, when the comparison result of a processor number is made forcibly dissident, processing for an address array 23 is carried out with a cache coincidence processing request signal 103 from a system controller 2 and a stored address 104 irrelevantly to the comparison result of a comparator 12. Therefore, the cache coincidence processing is carried out similarly to a case wherein a processor number 105 from the system controller 2 indicates the processor number of another device. Consequently, the cache coincidence processing unit can be evaluated without putting other processors except this device in actual operation.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INFORMATION PROCESSOR |
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