TIMING SIGNAL GENERATING SYSTEM FOR MEMORY DEVICE

PURPOSE:To contrive the simplification of a timing signal generating circuit by generating a signal, the inverse of CAS supplied to a memory element by adopting OR of a R/WCAS signal generated later than a signal, the inverse of RAS and a refreshing signal at the signal, the inverse of CAS generating circuit. CONSTITUTION:Signal, the inverse of CAS generating circuit 9 generates R/ WCAS signal (f) according to a stage signal (d), adopting the OR of the R/ WCAS signal (f) and the refreshing signal (c) at an OR gate 10, the output of the OR gate 10 is inputted to an input, the inverse of the CAS of the memory element 1 as a signal (g), the inverse of the CAS. Consequently, even in the case of the refreshing operating time, the signal, the inverse of CAS generating circuit 9 generates R/WCAS signal (f) at the later timing than the signal (e), the inverse of RAS, but as the inverse of CAS to the memory element 1 is decided by to be setting the refreshing signal, the inverse of CAS.BEFORE. the inverse of RAS refresh operation are attained. In such a manner, the memory device can be shared with the timing signal generating circuit, and the control circuit is simplified.