SUBSYSTEM CYCLE OF WRITE-READ/ WRITE-PASS MEMORY

SUBSYSTEM CYCLE OF WRITE-READ/ WRITE-PASS MEMORY

PURPOSE: To shorten the latency of storage device read by transferring data requested by a selected CPU to a system control unit(SCU) and checking the validity of data to transfer the data to the requesting CPU and writing it in a selected address of the main storage device of the SCU. CONSTITUTION:...

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Hauptverfasser: JIEIMUZU II TETSUSARI, MAIKERU EI GAGURIARUDO, JIYON JIEI RINKU, KUMAA CHINASUWAMII
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator JIEIMUZU II TETSUSARI
MAIKERU EI GAGURIARUDO
JIYON JIEI RINKU
KUMAA CHINASUWAMII
description PURPOSE: To shorten the latency of storage device read by transferring data requested by a selected CPU to a system control unit(SCU) and checking the validity of data to transfer the data to the requesting CPU and writing it in a selected address of the main storage device of the SCU. CONSTITUTION: In the 'write-read' cycle, only the valid part of data transferred to an SCU 4 in response to the data request from one of CPUs 12 requesting data is written in a main storage device 6 of the SCU, and on the other hand, all of data requested by one of CPUs 12 requesting data is read out from the main storage device of the SCU. Read data is data written in the main storage device 6 of the SCU and includes the valid part of data read by the SCU 4. Thus, the latency of storage device read is shortened in the case that two independent commands and two complete data transfer timing cycles for the main storage device of the SCU 4 are required.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SUBSYSTEM CYCLE OF WRITE-READ/ WRITE-PASS MEMORY
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