SYNCHRONOUS CIRCUIT

PURPOSE:To shorten the holding time of an asynchronous input signal with respect to a clock signal by fetching the asynchronous input signal from the input clock signal at a 1st stage circuit and outputting a signal synchronized with an internal clock signal. CONSTITUTION:The 1st stage logic circuit 6 consists of an AND/NOR gate, to which an asynchronous input signal I and an input clock signal phi are inputted. The asynchronous input signal I is fetched when the input clock signal phiis at a high level, and the 1st stage logic circuit 6 holds and outputs the data at the fall of the input clock signal phi for a period when the input clock signal phi is at a low level. The next stage logic circuit 7 consists of an OR/ NAND gate, which receives the 1st stage output signal the input clock signal phiand the internal clock signal phi2, fetches the 1st stage output for a period when the input clock signal phi is at a low level and the internal clock signal phi2 is at a high level and outputs an output '0' synchronously with the internal clock signal phi2. Thus, the holding time of the asynchronous input signal I with respect to the clock signal is shortened.