GENERATING METHOD FOR TIMING SIGNAL FOR TELEVISION

PURPOSE:To allow an oscillation element in a frequency being a half of that of a conventional element to cope with the processing, to reduce the operating current and to facilitate noise countermeasures by suppressing the maximum operating frequency twice the subcarrier frequency. CONSTITUTION:A bas...

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description PURPOSE:To allow an oscillation element in a frequency being a half of that of a conventional element to cope with the processing, to reduce the operating current and to facilitate noise countermeasures by suppressing the maximum operating frequency twice the subcarrier frequency. CONSTITUTION:A basic signal K having a frequency being twice the subcarrier frequency fSC is fed from a crystal oscillator 2 to a frequency divider 4, fed to a synchronizing counter 41 to obtain 9-bit outputs Q0-Q9. AND 42 of a prescribed output is fed to a D-FF 43. A clock input being the inversion of the basic signal K is fed. The output Q is fed to a D-FF 45 and the signal K is used as the clock. Thus, 2fSC is subject to 1/455 frequency division to obtain a horizontal synchronizing signal H1 of a horizontal frequency fH. Outputs Q0-Q9 are extracted by an auxiliary signal generating circuit 6, inverted to take AND 66, inputted to the D-FF 67, the signal K is inverted and used as the clock to form an auxiliary signal H2 with a phase shift of a half period with respect to the H1. The signals H1, H2 are ORed (8). When the output H0 is subject to 1/525 frequency division, a vertical synchronizing signal V is obtained and the maximum operating frequency fV is suppressed to 2fSC.
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CONSTITUTION:A basic signal K having a frequency being twice the subcarrier frequency fSC is fed from a crystal oscillator 2 to a frequency divider 4, fed to a synchronizing counter 41 to obtain 9-bit outputs Q0-Q9. AND 42 of a prescribed output is fed to a D-FF 43. A clock input being the inversion of the basic signal K is fed. The output Q is fed to a D-FF 45 and the signal K is used as the clock. Thus, 2fSC is subject to 1/455 frequency division to obtain a horizontal synchronizing signal H1 of a horizontal frequency fH. Outputs Q0-Q9 are extracted by an auxiliary signal generating circuit 6, inverted to take AND 66, inputted to the D-FF 67, the signal K is inverted and used as the clock to form an auxiliary signal H2 with a phase shift of a half period with respect to the H1. The signals H1, H2 are ORed (8). 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CONSTITUTION:A basic signal K having a frequency being twice the subcarrier frequency fSC is fed from a crystal oscillator 2 to a frequency divider 4, fed to a synchronizing counter 41 to obtain 9-bit outputs Q0-Q9. AND 42 of a prescribed output is fed to a D-FF 43. A clock input being the inversion of the basic signal K is fed. The output Q is fed to a D-FF 45 and the signal K is used as the clock. Thus, 2fSC is subject to 1/455 frequency division to obtain a horizontal synchronizing signal H1 of a horizontal frequency fH. Outputs Q0-Q9 are extracted by an auxiliary signal generating circuit 6, inverted to take AND 66, inputted to the D-FF 67, the signal K is inverted and used as the clock to form an auxiliary signal H2 with a phase shift of a half period with respect to the H1. The signals H1, H2 are ORed (8). When the output H0 is subject to 1/525 frequency division, a vertical synchronizing signal V is obtained and the maximum operating frequency fV is suppressed to 2fSC.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
title GENERATING METHOD FOR TIMING SIGNAL FOR TELEVISION
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