BUFFER AMPLIFIER
PURPOSE:To eliminate variation in input capacity even if the voltage of an input signal varies by detecting the output voltage of an impedance converting means by a voltage detecting means and controlling the power source of the impedance converting means by a voltage control means controlled with t...
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creator | YAMAGUCHI YUJI KOYANAGI NOBUO |
description | PURPOSE:To eliminate variation in input capacity even if the voltage of an input signal varies by detecting the output voltage of an impedance converting means by a voltage detecting means and controlling the power source of the impedance converting means by a voltage control means controlled with the output of this voltage detecting means. CONSTITUTION:The input signal is impressed to the gate of an PET 101. One terminal of a resistance 102 is connected to the source of the FET 101, and the other terminal is connected to the drain of an FET 103. A resistance 104 is connected between the source and gate of the FET 103. Further, its source is connected to a negative power source VSS. An output is led out of the drain of the FET 103. A transistor(TR) 11 constitutes a voltage detecting means. The collector of the TR 11 is connected to the negative power source VSS and the base is connected to the output of the impedance converting means 10. A voltage control means 12 consists of a TR 121, a constant current source 122, and a resistance 123. The collector of the TR 121 is connected to the plus electrode VDD and the emitter is connected to the drain of the FET 101. |
format | Patent |
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CONSTITUTION:The input signal is impressed to the gate of an PET 101. One terminal of a resistance 102 is connected to the source of the FET 101, and the other terminal is connected to the drain of an FET 103. A resistance 104 is connected between the source and gate of the FET 103. Further, its source is connected to a negative power source VSS. An output is led out of the drain of the FET 103. A transistor(TR) 11 constitutes a voltage detecting means. The collector of the TR 11 is connected to the negative power source VSS and the base is connected to the output of the impedance converting means 10. A voltage control means 12 consists of a TR 121, a constant current source 122, and a resistance 123. The collector of the TR 121 is connected to the plus electrode VDD and the emitter is connected to the drain of the FET 101.</description><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19890711&DB=EPODOC&CC=JP&NR=H01175403A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19890711&DB=EPODOC&CC=JP&NR=H01175403A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAGUCHI YUJI</creatorcontrib><creatorcontrib>KOYANAGI NOBUO</creatorcontrib><title>BUFFER AMPLIFIER</title><description>PURPOSE:To eliminate variation in input capacity even if the voltage of an input signal varies by detecting the output voltage of an impedance converting means by a voltage detecting means and controlling the power source of the impedance converting means by a voltage control means controlled with the output of this voltage detecting means. CONSTITUTION:The input signal is impressed to the gate of an PET 101. One terminal of a resistance 102 is connected to the source of the FET 101, and the other terminal is connected to the drain of an FET 103. A resistance 104 is connected between the source and gate of the FET 103. Further, its source is connected to a negative power source VSS. An output is led out of the drain of the FET 103. A transistor(TR) 11 constitutes a voltage detecting means. The collector of the TR 11 is connected to the negative power source VSS and the base is connected to the output of the impedance converting means 10. A voltage control means 12 consists of a TR 121, a constant current source 122, and a resistance 123. The collector of the TR 121 is connected to the plus electrode VDD and the emitter is connected to the drain of the FET 101.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1989</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBBwCnVzcw1ScPQN8PF083QN4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgaGhuamJgbGjsbEqAEAAEIdlg</recordid><startdate>19890711</startdate><enddate>19890711</enddate><creator>YAMAGUCHI YUJI</creator><creator>KOYANAGI NOBUO</creator><scope>EVB</scope></search><sort><creationdate>19890711</creationdate><title>BUFFER AMPLIFIER</title><author>YAMAGUCHI YUJI ; KOYANAGI NOBUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH01175403A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1989</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAGUCHI YUJI</creatorcontrib><creatorcontrib>KOYANAGI NOBUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAGUCHI YUJI</au><au>KOYANAGI NOBUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUFFER AMPLIFIER</title><date>1989-07-11</date><risdate>1989</risdate><abstract>PURPOSE:To eliminate variation in input capacity even if the voltage of an input signal varies by detecting the output voltage of an impedance converting means by a voltage detecting means and controlling the power source of the impedance converting means by a voltage control means controlled with the output of this voltage detecting means. CONSTITUTION:The input signal is impressed to the gate of an PET 101. One terminal of a resistance 102 is connected to the source of the FET 101, and the other terminal is connected to the drain of an FET 103. A resistance 104 is connected between the source and gate of the FET 103. Further, its source is connected to a negative power source VSS. An output is led out of the drain of the FET 103. A transistor(TR) 11 constitutes a voltage detecting means. The collector of the TR 11 is connected to the negative power source VSS and the base is connected to the output of the impedance converting means 10. A voltage control means 12 consists of a TR 121, a constant current source 122, and a resistance 123. The collector of the TR 121 is connected to the plus electrode VDD and the emitter is connected to the drain of the FET 101.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | AMPLIFIERS BASIC ELECTRONIC CIRCUITRY ELECTRICITY |
title | BUFFER AMPLIFIER |
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