JP2906073B
A circuit device including a DC characteristic test circuit is arranged to have a reset signal supplied via a reset signal input terminal for resetting a testee circuit to be subjected to a DC characteristic test; and to include an output buffer circuit which receives a predetermined output signal o...
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| creator | ISHIZUKA TAKAHARU |
| description | A circuit device including a DC characteristic test circuit is arranged to have a reset signal supplied via a reset signal input terminal for resetting a testee circuit to be subjected to a DC characteristic test; and to include an output buffer circuit which receives a predetermined output signal of the testee circuit and the reset signal supplied from the reset signal input terminal. The arrangement enables the DC characteristic test to be quickly carried out on the circuit device at a low cost and without increasing the number of terminals required for the test. |
| format | Patent |
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The arrangement enables the DC characteristic test to be quickly carried out on the circuit device at a low cost and without increasing the number of terminals required for the test.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990614&DB=EPODOC&CC=JP&NR=2906073B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990614&DB=EPODOC&CC=JP&NR=2906073B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ISHIZUKA TAKAHARU</creatorcontrib><title>JP2906073B</title><description>A circuit device including a DC characteristic test circuit is arranged to have a reset signal supplied via a reset signal input terminal for resetting a testee circuit to be subjected to a DC characteristic test; and to include an output buffer circuit which receives a predetermined output signal of the testee circuit and the reset signal supplied from the reset signal input terminal. The arrangement enables the DC characteristic test to be quickly carried out on the circuit device at a low cost and without increasing the number of terminals required for the test.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZODyCjCyNDAzMDd24mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8QgNTkbGxKgBACWjG2o</recordid><startdate>19990614</startdate><enddate>19990614</enddate><creator>ISHIZUKA TAKAHARU</creator><scope>EVB</scope></search><sort><creationdate>19990614</creationdate><title>JP2906073B</title><author>ISHIZUKA TAKAHARU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2906073BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>ISHIZUKA TAKAHARU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ISHIZUKA TAKAHARU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JP2906073B</title><date>1999-06-14</date><risdate>1999</risdate><abstract>A circuit device including a DC characteristic test circuit is arranged to have a reset signal supplied via a reset signal input terminal for resetting a testee circuit to be subjected to a DC characteristic test; and to include an output buffer circuit which receives a predetermined output signal of the testee circuit and the reset signal supplied from the reset signal input terminal. The arrangement enables the DC characteristic test to be quickly carried out on the circuit device at a low cost and without increasing the number of terminals required for the test.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | JP2906073B |
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