JP2871610B

A zig-zag and alternate scan conversion circuit for encoding/decoding videos which is structured only by logic circuits using a regularity of scan address patterns, thereby achieving an improvement in processing speed and a reduction in area. The circuit includes a zig-zag and alternate scan address generating unit for receiving a start signal, a basic operation clock signal, and a control signal indicative of whether the scan pattern of input data is a zig-zag scan pattern or an alternate scan pattern, and executing an operation for writing the input data on a RAM and reading them from the RAM based on the received signals, a raster address generating unit for receiving the same signals as those received in the zig-zag and alternate scan address generating unit and executing a writing/reading operation of the input data, a pair of multiplexor units each for appropriately selecting an address signal from the address generating units; and a latch unit for outputting address signals selected from the multiplexor units while controlling the timing of the address signals. The circuit can be applied to systems requiring high-speed data processing such as B-ISDN terminals and high definition televisions. The circuit can also be easily used in systems including circuits designed in the form of a VLSI which will be used as an application-specific integrated circuit (ASIC).