JP2862424B

PURPOSE:To continue the operation of a processor unit provided with cache memory from the occurrence to the restoration of a fault after the fault occurs on the system on one side of a multiplexed bus. CONSTITUTION:When a bus 210 is disabled, the cache memory 411 is separated logically from this information processor. During that time, the processor unit 110 continues its operation by the cache memory 412. When the bus 210 can be used again, all the data in which only the cache memory is reloaded and no main storage is reloaded are stored in the main storage of the cache memory 412 after the copy of data in the main storage is completed and the cache memory 412 is invalidated by inhibiting its operation, and the separate state of the cache memory 411 is cancelled, and the operation inhibition of the cache memory is cancelled, then, an ordinary operation can be continued.