SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF
To provide a semiconductor element with improved electrical characteristics.SOLUTION: The present invention relates to a semiconductor element and a manufacturing method thereof, in more specifically, the semiconductor element comprises a substrate including an active pattern, a channel pattern on t...
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creator | YU HYUN-KWAN LEE SUNYOUNG PARK HYUNWOO |
description | To provide a semiconductor element with improved electrical characteristics.SOLUTION: The present invention relates to a semiconductor element and a manufacturing method thereof, in more specifically, the semiconductor element comprises a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern linked to the channel pattern, a gate electrode on the channel pattern, and a gate insulation film between the channel pattern and the gate electrode. The gate electrode includes an inner electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other. The gate insulation film includes a high dielectric film surrounding the inner electrode of the gate electrode and an inner spacer on the high dielectric film. The inner spacer includes a first horizontal portion between the high dielectric film and the second semiconductor pattern, a first vertical portion between the high dielectric film and the source/drain pattern, and a first corner portion connecting the first horizontal portion and the first vertical portion to each other.SELECTED DRAWING: Figure 6A
【課題】電気的特性が向上された半導体素子を提供する。【解決手段】本発明は半導体素子及びその製造方法に関し、さらに詳細には、活性パターンを含む基板、前記活性パターン上のチャンネルパターン、前記チャンネルパターンに連結されたソース/ドレインパターン、前記チャンネルパターン上のゲート電極、及び前記チャンネルパターンと前記ゲート電極との間のゲート絶縁膜を含む。前記ゲート電極は互いに隣接する第1半導体パターンと第2半導体パターンとの間に介在された内側電極を含み、前記ゲート絶縁膜は、前記ゲート電極の前記内側電極を囲む高誘電膜及び前記高誘電膜上の内側スペーサーを含む。前記内側スペーサーは前記高誘電膜と前記第2半導体パターンとの間の第1水平部分、前記高誘電膜と前記ソース/ドレインパターンとの間の第1垂直部分、及び前記第1水平部分と前記第1垂直部分を互いに連結する第1コーナー部分を含む。【選択図】図6A |
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【課題】電気的特性が向上された半導体素子を提供する。【解決手段】本発明は半導体素子及びその製造方法に関し、さらに詳細には、活性パターンを含む基板、前記活性パターン上のチャンネルパターン、前記チャンネルパターンに連結されたソース/ドレインパターン、前記チャンネルパターン上のゲート電極、及び前記チャンネルパターンと前記ゲート電極との間のゲート絶縁膜を含む。前記ゲート電極は互いに隣接する第1半導体パターンと第2半導体パターンとの間に介在された内側電極を含み、前記ゲート絶縁膜は、前記ゲート電極の前記内側電極を囲む高誘電膜及び前記高誘電膜上の内側スペーサーを含む。前記内側スペーサーは前記高誘電膜と前記第2半導体パターンとの間の第1水平部分、前記高誘電膜と前記ソース/ドレインパターンとの間の第1垂直部分、及び前記第1水平部分と前記第1垂直部分を互いに連結する第1コーナー部分を含む。【選択図】図6A</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240718&DB=EPODOC&CC=JP&NR=2024097310A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240718&DB=EPODOC&CC=JP&NR=2024097310A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YU HYUN-KWAN</creatorcontrib><creatorcontrib>LEE SUNYOUNG</creatorcontrib><creatorcontrib>PARK HYUNWOO</creatorcontrib><title>SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF</title><description>To provide a semiconductor element with improved electrical characteristics.SOLUTION: The present invention relates to a semiconductor element and a manufacturing method thereof, in more specifically, the semiconductor element comprises a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern linked to the channel pattern, a gate electrode on the channel pattern, and a gate insulation film between the channel pattern and the gate electrode. The gate electrode includes an inner electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other. The gate insulation film includes a high dielectric film surrounding the inner electrode of the gate electrode and an inner spacer on the high dielectric film. The inner spacer includes a first horizontal portion between the high dielectric film and the second semiconductor pattern, a first vertical portion between the high dielectric film and the source/drain pattern, and a first corner portion connecting the first horizontal portion and the first vertical portion to each other.SELECTED DRAWING: Figure 6A
【課題】電気的特性が向上された半導体素子を提供する。【解決手段】本発明は半導体素子及びその製造方法に関し、さらに詳細には、活性パターンを含む基板、前記活性パターン上のチャンネルパターン、前記チャンネルパターンに連結されたソース/ドレインパターン、前記チャンネルパターン上のゲート電極、及び前記チャンネルパターンと前記ゲート電極との間のゲート絶縁膜を含む。前記ゲート電極は互いに隣接する第1半導体パターンと第2半導体パターンとの間に介在された内側電極を含み、前記ゲート絶縁膜は、前記ゲート電極の前記内側電極を囲む高誘電膜及び前記高誘電膜上の内側スペーサーを含む。前記内側スペーサーは前記高誘電膜と前記第2半導体パターンとの間の第1水平部分、前記高誘電膜と前記ソース/ドレインパターンとの間の第1垂直部分、及び前記第1水平部分と前記第1垂直部分を互いに連結する第1コーナー部分を含む。【選択図】図6A</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALdvX1dPb3cwl1DvEPUnD1cfV19QtRcPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkYmBpbmxoYGjsZEKQIAfBsohw</recordid><startdate>20240718</startdate><enddate>20240718</enddate><creator>YU HYUN-KWAN</creator><creator>LEE SUNYOUNG</creator><creator>PARK HYUNWOO</creator><scope>EVB</scope></search><sort><creationdate>20240718</creationdate><title>SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF</title><author>YU HYUN-KWAN ; LEE SUNYOUNG ; PARK HYUNWOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024097310A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YU HYUN-KWAN</creatorcontrib><creatorcontrib>LEE SUNYOUNG</creatorcontrib><creatorcontrib>PARK HYUNWOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YU HYUN-KWAN</au><au>LEE SUNYOUNG</au><au>PARK HYUNWOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF</title><date>2024-07-18</date><risdate>2024</risdate><abstract>To provide a semiconductor element with improved electrical characteristics.SOLUTION: The present invention relates to a semiconductor element and a manufacturing method thereof, in more specifically, the semiconductor element comprises a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern linked to the channel pattern, a gate electrode on the channel pattern, and a gate insulation film between the channel pattern and the gate electrode. The gate electrode includes an inner electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other. The gate insulation film includes a high dielectric film surrounding the inner electrode of the gate electrode and an inner spacer on the high dielectric film. The inner spacer includes a first horizontal portion between the high dielectric film and the second semiconductor pattern, a first vertical portion between the high dielectric film and the source/drain pattern, and a first corner portion connecting the first horizontal portion and the first vertical portion to each other.SELECTED DRAWING: Figure 6A
【課題】電気的特性が向上された半導体素子を提供する。【解決手段】本発明は半導体素子及びその製造方法に関し、さらに詳細には、活性パターンを含む基板、前記活性パターン上のチャンネルパターン、前記チャンネルパターンに連結されたソース/ドレインパターン、前記チャンネルパターン上のゲート電極、及び前記チャンネルパターンと前記ゲート電極との間のゲート絶縁膜を含む。前記ゲート電極は互いに隣接する第1半導体パターンと第2半導体パターンとの間に介在された内側電極を含み、前記ゲート絶縁膜は、前記ゲート電極の前記内側電極を囲む高誘電膜及び前記高誘電膜上の内側スペーサーを含む。前記内側スペーサーは前記高誘電膜と前記第2半導体パターンとの間の第1水平部分、前記高誘電膜と前記ソース/ドレインパターンとの間の第1垂直部分、及び前記第1水平部分と前記第1垂直部分を互いに連結する第1コーナー部分を含む。【選択図】図6A</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF |
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