CLOCK OUTPUT PHASING CONTROL CIRCUIT
To solve a problem in which it is difficult to select whether two clock outputs from a redundant clock transmission panel are to be in the same phase or in opposite phases.SOLUTION: Each of two clock transmission panels of a clock output phasing control circuit is composed of two clock transmission...
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| creator | TAMAI HIDEAKI |
| description | To solve a problem in which it is difficult to select whether two clock outputs from a redundant clock transmission panel are to be in the same phase or in opposite phases.SOLUTION: Each of two clock transmission panels of a clock output phasing control circuit is composed of two clock transmission panels forming a redundant configuration of 0 system and 1 system includes a startup time adjustment unit that makes a difference in a startup time of the two clock transmission panels, a frequency division unit that generates both a positive phase output and a negative phase output of the clock divided by 2, and a selector that selects either the positive phase output or the negative phase output. The clock output phasing control circuit further includes a supervisory control circuit that controls the selector.SELECTED DRAWING: Figure 1
【課題】冗長構成がとられているクロック送信パネルから出力される２つのクロック出力を、同位相にするか逆位相にするかを選択することが困難であること。【解決手段】０系と１系との冗長構成を形成する２つのクロック送信パネルを含んで構成されるクロック出力位相合わせ制御回路の２つの上記クロック送信パネルのそれぞれは、２つの前記クロック送信パネルの起動時間に差をつける起動時間調整部と、２分周したクロックの正相出力と逆相出力の両方を生成する分周部と、上記正相出力と上記逆相出力の何れか一方を選択するセレクタと、を備える。また、クロック出力位相合わせ制御回路は、上記セレクタを制御する監視制御回路をさらに備える。【選択図】図１ |
| format | Patent |
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【課題】冗長構成がとられているクロック送信パネルから出力される２つのクロック出力を、同位相にするか逆位相にするかを選択することが困難であること。【解決手段】０系と１系との冗長構成を形成する２つのクロック送信パネルを含んで構成されるクロック出力位相合わせ制御回路の２つの上記クロック送信パネルのそれぞれは、２つの前記クロック送信パネルの起動時間に差をつける起動時間調整部と、２分周したクロックの正相出力と逆相出力の両方を生成する分周部と、上記正相出力と上記逆相出力の何れか一方を選択するセレクタと、を備える。また、クロック出力位相合わせ制御回路は、上記セレクタを制御する監視制御回路をさらに備える。【選択図】図１</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240514&DB=EPODOC&CC=JP&NR=2024064073A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240514&DB=EPODOC&CC=JP&NR=2024064073A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TAMAI HIDEAKI</creatorcontrib><title>CLOCK OUTPUT PHASING CONTROL CIRCUIT</title><description>To solve a problem in which it is difficult to select whether two clock outputs from a redundant clock transmission panel are to be in the same phase or in opposite phases.SOLUTION: Each of two clock transmission panels of a clock output phasing control circuit is composed of two clock transmission panels forming a redundant configuration of 0 system and 1 system includes a startup time adjustment unit that makes a difference in a startup time of the two clock transmission panels, a frequency division unit that generates both a positive phase output and a negative phase output of the clock divided by 2, and a selector that selects either the positive phase output or the negative phase output. The clock output phasing control circuit further includes a supervisory control circuit that controls the selector.SELECTED DRAWING: Figure 1
【課題】冗長構成がとられているクロック送信パネルから出力される２つのクロック出力を、同位相にするか逆位相にするかを選択することが困難であること。【解決手段】０系と１系との冗長構成を形成する２つのクロック送信パネルを含んで構成されるクロック出力位相合わせ制御回路の２つの上記クロック送信パネルのそれぞれは、２つの前記クロック送信パネルの起動時間に差をつける起動時間調整部と、２分周したクロックの正相出力と逆相出力の両方を生成する分周部と、上記正相出力と上記逆相出力の何れか一方を選択するセレクタと、を備える。また、クロック出力位相合わせ制御回路は、上記セレクタを制御する監視制御回路をさらに備える。【選択図】図１</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBx9vF39lbwDw0JCA1RCPBwDPb0c1dw9vcLCfL3UXD2DHIO9QzhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkYmBmYmBubGjsZEKQIA0cgjkg</recordid><startdate>20240514</startdate><enddate>20240514</enddate><creator>TAMAI HIDEAKI</creator><scope>EVB</scope></search><sort><creationdate>20240514</creationdate><title>CLOCK OUTPUT PHASING CONTROL CIRCUIT</title><author>TAMAI HIDEAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024064073A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>TAMAI HIDEAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAMAI HIDEAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CLOCK OUTPUT PHASING CONTROL CIRCUIT</title><date>2024-05-14</date><risdate>2024</risdate><abstract>To solve a problem in which it is difficult to select whether two clock outputs from a redundant clock transmission panel are to be in the same phase or in opposite phases.SOLUTION: Each of two clock transmission panels of a clock output phasing control circuit is composed of two clock transmission panels forming a redundant configuration of 0 system and 1 system includes a startup time adjustment unit that makes a difference in a startup time of the two clock transmission panels, a frequency division unit that generates both a positive phase output and a negative phase output of the clock divided by 2, and a selector that selects either the positive phase output or the negative phase output. The clock output phasing control circuit further includes a supervisory control circuit that controls the selector.SELECTED DRAWING: Figure 1
【課題】冗長構成がとられているクロック送信パネルから出力される２つのクロック出力を、同位相にするか逆位相にするかを選択することが困難であること。【解決手段】０系と１系との冗長構成を形成する２つのクロック送信パネルを含んで構成されるクロック出力位相合わせ制御回路の２つの上記クロック送信パネルのそれぞれは、２つの前記クロック送信パネルの起動時間に差をつける起動時間調整部と、２分周したクロックの正相出力と逆相出力の両方を生成する分周部と、上記正相出力と上記逆相出力の何れか一方を選択するセレクタと、を備える。また、クロック出力位相合わせ制御回路は、上記セレクタを制御する監視制御回路をさらに備える。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | CLOCK OUTPUT PHASING CONTROL CIRCUIT |
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