WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE
To provide a wiring board capable of increasing connection reliability when connected to semiconductor chips.SOLUTION: A wiring board has: an insulation layer; an electrode that is provided in the insulation layer and in which a first face is exposed from the insulation layer; and an external connec...
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creator | AIZAWA MITSUHIRO MURAYAMA HIROSHI |
description | To provide a wiring board capable of increasing connection reliability when connected to semiconductor chips.SOLUTION: A wiring board has: an insulation layer; an electrode that is provided in the insulation layer and in which a first face is exposed from the insulation layer; and an external connection terminal that is provided on the first face of the electrode. The electrode comprises a recess on the first face. The external connection terminal includes a first conductor filling the recess, and a second conductor provided on the first conductor. The first conductor has a melting point higher than that of the second conductor.SELECTED DRAWING: Figure 1
【課題】半導体チップと接続する場合の接続信頼性を向上可能な配線基板を提供する。【解決手段】本配線基板は、絶縁層と、前記絶縁層に設けられ、第1の面が前記絶縁層から露出する電極と、前記電極の前記第1の面に設けられた外部接続端子と、を有し、前記電極は、前記第1の面に凹部を備え、前記外部接続端子は、前記凹部を埋める第1導体と、前記第1導体上に設けられた第2導体と、を含み、前記第1導体の融点は、前記第2導体の融点よりも高い。【選択図】図1 |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2024061960A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2024061960A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2024061960A3</originalsourceid><addsrcrecordid>eNrjZHAL9wzy9HNXcPJ3DHLRUXBzdArydHYM8fT3U_B1DfHwd1Hwd1MI8XBVCHb0ddVRcPRzUQh29fV09vdzCXUO8Q9ScHEN83R25WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgZGJgZmhpZmBo7GRCkCAL6yLC4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>AIZAWA MITSUHIRO ; MURAYAMA HIROSHI</creator><creatorcontrib>AIZAWA MITSUHIRO ; MURAYAMA HIROSHI</creatorcontrib><description>To provide a wiring board capable of increasing connection reliability when connected to semiconductor chips.SOLUTION: A wiring board has: an insulation layer; an electrode that is provided in the insulation layer and in which a first face is exposed from the insulation layer; and an external connection terminal that is provided on the first face of the electrode. The electrode comprises a recess on the first face. The external connection terminal includes a first conductor filling the recess, and a second conductor provided on the first conductor. The first conductor has a melting point higher than that of the second conductor.SELECTED DRAWING: Figure 1
【課題】半導体チップと接続する場合の接続信頼性を向上可能な配線基板を提供する。【解決手段】本配線基板は、絶縁層と、前記絶縁層に設けられ、第1の面が前記絶縁層から露出する電極と、前記電極の前記第1の面に設けられた外部接続端子と、を有し、前記電極は、前記第1の面に凹部を備え、前記外部接続端子は、前記凹部を埋める第1導体と、前記第1導体上に設けられた第2導体と、を含み、前記第1導体の融点は、前記第2導体の融点よりも高い。【選択図】図1</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240509&DB=EPODOC&CC=JP&NR=2024061960A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240509&DB=EPODOC&CC=JP&NR=2024061960A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AIZAWA MITSUHIRO</creatorcontrib><creatorcontrib>MURAYAMA HIROSHI</creatorcontrib><title>WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE</title><description>To provide a wiring board capable of increasing connection reliability when connected to semiconductor chips.SOLUTION: A wiring board has: an insulation layer; an electrode that is provided in the insulation layer and in which a first face is exposed from the insulation layer; and an external connection terminal that is provided on the first face of the electrode. The electrode comprises a recess on the first face. The external connection terminal includes a first conductor filling the recess, and a second conductor provided on the first conductor. The first conductor has a melting point higher than that of the second conductor.SELECTED DRAWING: Figure 1
【課題】半導体チップと接続する場合の接続信頼性を向上可能な配線基板を提供する。【解決手段】本配線基板は、絶縁層と、前記絶縁層に設けられ、第1の面が前記絶縁層から露出する電極と、前記電極の前記第1の面に設けられた外部接続端子と、を有し、前記電極は、前記第1の面に凹部を備え、前記外部接続端子は、前記凹部を埋める第1導体と、前記第1導体上に設けられた第2導体と、を含み、前記第1導体の融点は、前記第2導体の融点よりも高い。【選択図】図1</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAL9wzy9HNXcPJ3DHLRUXBzdArydHYM8fT3U_B1DfHwd1Hwd1MI8XBVCHb0ddVRcPRzUQh29fV09vdzCXUO8Q9ScHEN83R25WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgZGJgZmhpZmBo7GRCkCAL6yLC4</recordid><startdate>20240509</startdate><enddate>20240509</enddate><creator>AIZAWA MITSUHIRO</creator><creator>MURAYAMA HIROSHI</creator><scope>EVB</scope></search><sort><creationdate>20240509</creationdate><title>WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE</title><author>AIZAWA MITSUHIRO ; MURAYAMA HIROSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024061960A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AIZAWA MITSUHIRO</creatorcontrib><creatorcontrib>MURAYAMA HIROSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AIZAWA MITSUHIRO</au><au>MURAYAMA HIROSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE</title><date>2024-05-09</date><risdate>2024</risdate><abstract>To provide a wiring board capable of increasing connection reliability when connected to semiconductor chips.SOLUTION: A wiring board has: an insulation layer; an electrode that is provided in the insulation layer and in which a first face is exposed from the insulation layer; and an external connection terminal that is provided on the first face of the electrode. The electrode comprises a recess on the first face. The external connection terminal includes a first conductor filling the recess, and a second conductor provided on the first conductor. The first conductor has a melting point higher than that of the second conductor.SELECTED DRAWING: Figure 1
【課題】半導体チップと接続する場合の接続信頼性を向上可能な配線基板を提供する。【解決手段】本配線基板は、絶縁層と、前記絶縁層に設けられ、第1の面が前記絶縁層から露出する電極と、前記電極の前記第1の面に設けられた外部接続端子と、を有し、前記電極は、前記第1の面に凹部を備え、前記外部接続端子は、前記凹部を埋める第1導体と、前記第1導体上に設けられた第2導体と、を含み、前記第1導体の融点は、前記第2導体の融点よりも高い。【選択図】図1</abstract><oa>free_for_read</oa></addata></record> |
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language | eng ; jpn |
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subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | WIRING BOARD, FABRICATION METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE |
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