MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF
To provide a memory device structure and a manufacturing method thereof.SOLUTION: A method according to the present disclosure includes the steps of forming a bottom electrode layer above a substrate, forming an insulator layer above the bottom electrode layer, depositing a semiconductor layer inclu...
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| creator | HUANG KUOING ONG YI CHING TING YU-WEI TING YU WEI CHAN YAT HIN CHEN KUEN-YI |
| description | To provide a memory device structure and a manufacturing method thereof.SOLUTION: A method according to the present disclosure includes the steps of forming a bottom electrode layer above a substrate, forming an insulator layer above the bottom electrode layer, depositing a semiconductor layer including a plurality of portions having different thicknesses above the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer above the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack.SELECTED DRAWING: Figure 3
【課題】メモリ装置構造及びその製造方法を提供する。【解決手段】本開示による方法は、基板の上方に底部電極層を形成する工程と、底部電極層の上方に絶縁体層を形成する工程と、底部電極層の上方に異なる厚さを有する複数の部分を含む半導体層を堆積する工程と、半導体層の上方に強誘電体層を堆積する工程と、強誘電体層の上方に頂部電極層を形成する工程と、底部電極層、絶縁体層、半導体層、強誘電体層、及び頂部電極層をパターン化してメモリスタックを形成する工程と、を有する。【選択図】図３ |
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【課題】メモリ装置構造及びその製造方法を提供する。【解決手段】本開示による方法は、基板の上方に底部電極層を形成する工程と、底部電極層の上方に絶縁体層を形成する工程と、底部電極層の上方に異なる厚さを有する複数の部分を含む半導体層を堆積する工程と、半導体層の上方に強誘電体層を堆積する工程と、強誘電体層の上方に頂部電極層を形成する工程と、底部電極層、絶縁体層、半導体層、強誘電体層、及び頂部電極層をパターン化してメモリスタックを形成する工程と、を有する。【選択図】図３</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230922&DB=EPODOC&CC=JP&NR=2023133256A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230922&DB=EPODOC&CC=JP&NR=2023133256A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUANG KUOING</creatorcontrib><creatorcontrib>ONG YI CHING</creatorcontrib><creatorcontrib>TING YU-WEI</creatorcontrib><creatorcontrib>TING YU WEI</creatorcontrib><creatorcontrib>CHAN YAT HIN</creatorcontrib><creatorcontrib>CHEN KUEN-YI</creatorcontrib><title>MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF</title><description>To provide a memory device structure and a manufacturing method thereof.SOLUTION: A method according to the present disclosure includes the steps of forming a bottom electrode layer above a substrate, forming an insulator layer above the bottom electrode layer, depositing a semiconductor layer including a plurality of portions having different thicknesses above the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer above the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack.SELECTED DRAWING: Figure 3
【課題】メモリ装置構造及びその製造方法を提供する。【解決手段】本開示による方法は、基板の上方に底部電極層を形成する工程と、底部電極層の上方に絶縁体層を形成する工程と、底部電極層の上方に異なる厚さを有する複数の部分を含む半導体層を堆積する工程と、半導体層の上方に強誘電体層を堆積する工程と、強誘電体層の上方に頂部電極層を形成する工程と、底部電極層、絶縁体層、半導体層、強誘電体層、及び頂部電極層をパターン化してメモリスタックを形成する工程と、を有する。【選択図】図３</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwdfX1D4pUcHEN83R2VQgOCQp1DgkNclVw9HNR8HX0C3VzBPE9_dwVfF1DPPxdFEI8XINc_d14GFjTEnOKU3mhNDeDkptriLOHbmpBfnxqcUFicmpeakm8V4CRgZGxobGxkamZozFRigDObSkY</recordid><startdate>20230922</startdate><enddate>20230922</enddate><creator>HUANG KUOING</creator><creator>ONG YI CHING</creator><creator>TING YU-WEI</creator><creator>TING YU WEI</creator><creator>CHAN YAT HIN</creator><creator>CHEN KUEN-YI</creator><scope>EVB</scope></search><sort><creationdate>20230922</creationdate><title>MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF</title><author>HUANG KUOING ; ONG YI CHING ; TING YU-WEI ; TING YU WEI ; CHAN YAT HIN ; CHEN KUEN-YI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2023133256A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HUANG KUOING</creatorcontrib><creatorcontrib>ONG YI CHING</creatorcontrib><creatorcontrib>TING YU-WEI</creatorcontrib><creatorcontrib>TING YU WEI</creatorcontrib><creatorcontrib>CHAN YAT HIN</creatorcontrib><creatorcontrib>CHEN KUEN-YI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUANG KUOING</au><au>ONG YI CHING</au><au>TING YU-WEI</au><au>TING YU WEI</au><au>CHAN YAT HIN</au><au>CHEN KUEN-YI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF</title><date>2023-09-22</date><risdate>2023</risdate><abstract>To provide a memory device structure and a manufacturing method thereof.SOLUTION: A method according to the present disclosure includes the steps of forming a bottom electrode layer above a substrate, forming an insulator layer above the bottom electrode layer, depositing a semiconductor layer including a plurality of portions having different thicknesses above the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer above the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack.SELECTED DRAWING: Figure 3
【課題】メモリ装置構造及びその製造方法を提供する。【解決手段】本開示による方法は、基板の上方に底部電極層を形成する工程と、底部電極層の上方に絶縁体層を形成する工程と、底部電極層の上方に異なる厚さを有する複数の部分を含む半導体層を堆積する工程と、半導体層の上方に強誘電体層を堆積する工程と、強誘電体層の上方に頂部電極層を形成する工程と、底部電極層、絶縁体層、半導体層、強誘電体層、及び頂部電極層をパターン化してメモリスタックを形成する工程と、を有する。【選択図】図３</abstract><oa>free_for_read</oa></addata></record> |
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| title | MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF |
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