SEMICONDUCTOR DEVICE

To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed o...

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Hauptverfasser: NISHI KOICHI, TANAKA KOJI, SAKAI NORIKAZU, KANO TAKETOSHI, SONEDA SHINYA, FUDA MASANORI
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creator NISHI KOICHI
TANAKA KOJI
SAKAI NORIKAZU
KANO TAKETOSHI
SONEDA SHINYA
FUDA MASANORI
description To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed on a second principal surface of the semiconductor chip 1. The second main electrode 29 and the second control electrode pad 31 are bonded with first and second metal patterns 39 and 40 of an insulation substrate 36, respectively. Bonding parts of first and second wires 42 and 43 are overlapped with a junction of the second main electrode 29 or the second control electrode pad 31, in a plan view. A thickness of the first and second metal patterns 39 and 40 is equal to or less than 0.2 mm.SELECTED DRAWING: Figure 2 【課題】歩留まりが高く製造が容易な半導体装置を得る。【解決手段】半導体チップ1の第1の主面に第1の主電極10と第1の制御電極パッド15が形成されている。半導体チップ1の第2の主面に第2の主電極29と第2の制御電極パッド31が形成されている。第2の主電極29と第2の制御電極パッド31がそれぞれ絶縁基板36の第1及び第2の金属パターン39,40に接合されている。第1及び第2のワイヤ42,43のボンディング部は、平面視で第2の主電極29又は第2の制御電極パッド31の接合部に重なっている。第1及び第2の金属パターン39,40の厚みは0.2mm以下である。【選択図】図2
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2023087383A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2023087383A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2023087383A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRsYGFubGFsaOxkQpAgC-NB8m</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NISHI KOICHI ; TANAKA KOJI ; SAKAI NORIKAZU ; KANO TAKETOSHI ; SONEDA SHINYA ; FUDA MASANORI</creator><creatorcontrib>NISHI KOICHI ; TANAKA KOJI ; SAKAI NORIKAZU ; KANO TAKETOSHI ; SONEDA SHINYA ; FUDA MASANORI</creatorcontrib><description>To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed on a second principal surface of the semiconductor chip 1. The second main electrode 29 and the second control electrode pad 31 are bonded with first and second metal patterns 39 and 40 of an insulation substrate 36, respectively. Bonding parts of first and second wires 42 and 43 are overlapped with a junction of the second main electrode 29 or the second control electrode pad 31, in a plan view. A thickness of the first and second metal patterns 39 and 40 is equal to or less than 0.2 mm.SELECTED DRAWING: Figure 2 【課題】歩留まりが高く製造が容易な半導体装置を得る。【解決手段】半導体チップ1の第1の主面に第1の主電極10と第1の制御電極パッド15が形成されている。半導体チップ1の第2の主面に第2の主電極29と第2の制御電極パッド31が形成されている。第2の主電極29と第2の制御電極パッド31がそれぞれ絶縁基板36の第1及び第2の金属パターン39,40に接合されている。第1及び第2のワイヤ42,43のボンディング部は、平面視で第2の主電極29又は第2の制御電極パッド31の接合部に重なっている。第1及び第2の金属パターン39,40の厚みは0.2mm以下である。【選択図】図2</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230623&amp;DB=EPODOC&amp;CC=JP&amp;NR=2023087383A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230623&amp;DB=EPODOC&amp;CC=JP&amp;NR=2023087383A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NISHI KOICHI</creatorcontrib><creatorcontrib>TANAKA KOJI</creatorcontrib><creatorcontrib>SAKAI NORIKAZU</creatorcontrib><creatorcontrib>KANO TAKETOSHI</creatorcontrib><creatorcontrib>SONEDA SHINYA</creatorcontrib><creatorcontrib>FUDA MASANORI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed on a second principal surface of the semiconductor chip 1. The second main electrode 29 and the second control electrode pad 31 are bonded with first and second metal patterns 39 and 40 of an insulation substrate 36, respectively. Bonding parts of first and second wires 42 and 43 are overlapped with a junction of the second main electrode 29 or the second control electrode pad 31, in a plan view. A thickness of the first and second metal patterns 39 and 40 is equal to or less than 0.2 mm.SELECTED DRAWING: Figure 2 【課題】歩留まりが高く製造が容易な半導体装置を得る。【解決手段】半導体チップ1の第1の主面に第1の主電極10と第1の制御電極パッド15が形成されている。半導体チップ1の第2の主面に第2の主電極29と第2の制御電極パッド31が形成されている。第2の主電極29と第2の制御電極パッド31がそれぞれ絶縁基板36の第1及び第2の金属パターン39,40に接合されている。第1及び第2のワイヤ42,43のボンディング部は、平面視で第2の主電極29又は第2の制御電極パッド31の接合部に重なっている。第1及び第2の金属パターン39,40の厚みは0.2mm以下である。【選択図】図2</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRsYGFubGFsaOxkQpAgC-NB8m</recordid><startdate>20230623</startdate><enddate>20230623</enddate><creator>NISHI KOICHI</creator><creator>TANAKA KOJI</creator><creator>SAKAI NORIKAZU</creator><creator>KANO TAKETOSHI</creator><creator>SONEDA SHINYA</creator><creator>FUDA MASANORI</creator><scope>EVB</scope></search><sort><creationdate>20230623</creationdate><title>SEMICONDUCTOR DEVICE</title><author>NISHI KOICHI ; TANAKA KOJI ; SAKAI NORIKAZU ; KANO TAKETOSHI ; SONEDA SHINYA ; FUDA MASANORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2023087383A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NISHI KOICHI</creatorcontrib><creatorcontrib>TANAKA KOJI</creatorcontrib><creatorcontrib>SAKAI NORIKAZU</creatorcontrib><creatorcontrib>KANO TAKETOSHI</creatorcontrib><creatorcontrib>SONEDA SHINYA</creatorcontrib><creatorcontrib>FUDA MASANORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NISHI KOICHI</au><au>TANAKA KOJI</au><au>SAKAI NORIKAZU</au><au>KANO TAKETOSHI</au><au>SONEDA SHINYA</au><au>FUDA MASANORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2023-06-23</date><risdate>2023</risdate><abstract>To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed on a second principal surface of the semiconductor chip 1. The second main electrode 29 and the second control electrode pad 31 are bonded with first and second metal patterns 39 and 40 of an insulation substrate 36, respectively. Bonding parts of first and second wires 42 and 43 are overlapped with a junction of the second main electrode 29 or the second control electrode pad 31, in a plan view. A thickness of the first and second metal patterns 39 and 40 is equal to or less than 0.2 mm.SELECTED DRAWING: Figure 2 【課題】歩留まりが高く製造が容易な半導体装置を得る。【解決手段】半導体チップ1の第1の主面に第1の主電極10と第1の制御電極パッド15が形成されている。半導体チップ1の第2の主面に第2の主電極29と第2の制御電極パッド31が形成されている。第2の主電極29と第2の制御電極パッド31がそれぞれ絶縁基板36の第1及び第2の金属パターン39,40に接合されている。第1及び第2のワイヤ42,43のボンディング部は、平面視で第2の主電極29又は第2の制御電極パッド31の接合部に重なっている。第1及び第2の金属パターン39,40の厚みは0.2mm以下である。【選択図】図2</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE
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