SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NAKASHIBA YASUTAKA, KOSHIMIZU AKIRA, KAWAI TORU
Format: Patent
Sprache:eng ; jpn
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator NAKASHIBA YASUTAKA
KOSHIMIZU AKIRA
KAWAI TORU
description To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a part DF2 located inside the convex part CON. An n-drain area DR has an n-type impurity concentration higher than that of the n-type drift area DF. The n-type drift area DF is sandwiched between the n-drain area DR and a gate electrode GE. The n-drain area DR is arranged inside the convex part CON on the n-type drift area DF.SELECTED DRAWING: Figure 2 【課題】耐圧向上および小型化が容易な半導体装置およびその製造方法を提供する。【解決手段】半導体基板SBは、表面SUと、表面SUから上方に突き出す凸部CONとを有する。n型ドリフト領域DFは、凸部CONの内部に位置する部分DF2を有する。n-ドレイン領域DRは、n型ドリフト領域DFよりも高いn型不純物濃度を有し、平面視においてゲート電極GEとの間でn型ドリフト領域DFを挟み、かつ凸部CONの内部であってn型ドリフト領域DF上に配置されている。【選択図】図2
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2023031640A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2023031640A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2023031640A3</originalsourceid><addsrcrecordid>eNrjZLAKdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRcAOqCfFwVQh29HXlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkbGBsaGZiYGjsZEKQIA_bEpRA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME</title><source>esp@cenet</source><creator>NAKASHIBA YASUTAKA ; KOSHIMIZU AKIRA ; KAWAI TORU</creator><creatorcontrib>NAKASHIBA YASUTAKA ; KOSHIMIZU AKIRA ; KAWAI TORU</creatorcontrib><description>To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a part DF2 located inside the convex part CON. An n-drain area DR has an n-type impurity concentration higher than that of the n-type drift area DF. The n-type drift area DF is sandwiched between the n-drain area DR and a gate electrode GE. The n-drain area DR is arranged inside the convex part CON on the n-type drift area DF.SELECTED DRAWING: Figure 2 【課題】耐圧向上および小型化が容易な半導体装置およびその製造方法を提供する。【解決手段】半導体基板SBは、表面SUと、表面SUから上方に突き出す凸部CONとを有する。n型ドリフト領域DFは、凸部CONの内部に位置する部分DF2を有する。n-ドレイン領域DRは、n型ドリフト領域DFよりも高いn型不純物濃度を有し、平面視においてゲート電極GEとの間でn型ドリフト領域DFを挟み、かつ凸部CONの内部であってn型ドリフト領域DF上に配置されている。【選択図】図2</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230309&amp;DB=EPODOC&amp;CC=JP&amp;NR=2023031640A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230309&amp;DB=EPODOC&amp;CC=JP&amp;NR=2023031640A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAKASHIBA YASUTAKA</creatorcontrib><creatorcontrib>KOSHIMIZU AKIRA</creatorcontrib><creatorcontrib>KAWAI TORU</creatorcontrib><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME</title><description>To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a part DF2 located inside the convex part CON. An n-drain area DR has an n-type impurity concentration higher than that of the n-type drift area DF. The n-type drift area DF is sandwiched between the n-drain area DR and a gate electrode GE. The n-drain area DR is arranged inside the convex part CON on the n-type drift area DF.SELECTED DRAWING: Figure 2 【課題】耐圧向上および小型化が容易な半導体装置およびその製造方法を提供する。【解決手段】半導体基板SBは、表面SUと、表面SUから上方に突き出す凸部CONとを有する。n型ドリフト領域DFは、凸部CONの内部に位置する部分DF2を有する。n-ドレイン領域DRは、n型ドリフト領域DFよりも高いn型不純物濃度を有し、平面視においてゲート電極GEとの間でn型ドリフト領域DFを挟み、かつ凸部CONの内部であってn型ドリフト領域DF上に配置されている。【選択図】図2</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRcAOqCfFwVQh29HXlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkbGBsaGZiYGjsZEKQIA_bEpRA</recordid><startdate>20230309</startdate><enddate>20230309</enddate><creator>NAKASHIBA YASUTAKA</creator><creator>KOSHIMIZU AKIRA</creator><creator>KAWAI TORU</creator><scope>EVB</scope></search><sort><creationdate>20230309</creationdate><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME</title><author>NAKASHIBA YASUTAKA ; KOSHIMIZU AKIRA ; KAWAI TORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2023031640A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NAKASHIBA YASUTAKA</creatorcontrib><creatorcontrib>KOSHIMIZU AKIRA</creatorcontrib><creatorcontrib>KAWAI TORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAKASHIBA YASUTAKA</au><au>KOSHIMIZU AKIRA</au><au>KAWAI TORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME</title><date>2023-03-09</date><risdate>2023</risdate><abstract>To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a part DF2 located inside the convex part CON. An n-drain area DR has an n-type impurity concentration higher than that of the n-type drift area DF. The n-type drift area DF is sandwiched between the n-drain area DR and a gate electrode GE. The n-drain area DR is arranged inside the convex part CON on the n-type drift area DF.SELECTED DRAWING: Figure 2 【課題】耐圧向上および小型化が容易な半導体装置およびその製造方法を提供する。【解決手段】半導体基板SBは、表面SUと、表面SUから上方に突き出す凸部CONとを有する。n型ドリフト領域DFは、凸部CONの内部に位置する部分DF2を有する。n-ドレイン領域DRは、n型ドリフト領域DFよりも高いn型不純物濃度を有し、平面視においてゲート電極GEとの間でn型ドリフト領域DFを挟み、かつ凸部CONの内部であってn型ドリフト領域DF上に配置されている。【選択図】図2</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; jpn
recordid cdi_epo_espacenet_JP2023031640A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T16%3A56%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAKASHIBA%20YASUTAKA&rft.date=2023-03-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2023031640A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true