METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER
To provide a method and device for grinding a semiconductor wafer and a semiconductor wafer, capable of suppressing the occurrence of scratches when a ring-shaped protrusion on the outer periphery of a semiconductor wafer is ground.SOLUTION: There is provided a method for grinding a semiconductor wa...
Gespeichert in:
Hauptverfasser: | , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng ; jpn |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | NUMAGUCHI HIROYUKI ICHIKI HIDEHIKO TAMEFUJI MITOKO KATO KAZUSUKE HISATOKU SHINJI SATO YOHEI DOI YUKI HIDAKA YU |
description | To provide a method and device for grinding a semiconductor wafer and a semiconductor wafer, capable of suppressing the occurrence of scratches when a ring-shaped protrusion on the outer periphery of a semiconductor wafer is ground.SOLUTION: There is provided a method for grinding a semiconductor wafer for grinding a ring-shaped protrusion of a semiconductor wafer in which a flat part in a center on the rear face corresponding to a circuit formation area is thinned and the protrusion is formed on the outer periphery part on the rear face surrounding the flat part. In the method, a whetstone is tilted obliquely to be low on the outside of the semiconductor wafer to be brought into contact with the protrusion, and the protrusion is ground obliquely such that a difference between the height of the protrusion inside a ring after grinding and the height of the flat part is equal to or more than the particle diameter of particles generated during grinding.SELECTED DRAWING: Figure 7
【課題】半導体ウエハの外周部に在るリング状の凸部を研削する際に、スクラッチの発生を抑制することができる、半導体ウエハの研削方法、研削装置、及び半導体ウエハを提供する。【解決手段】回路形成領域に対応する裏面の中央の平坦部が薄化され、平坦部を取り囲む裏面の外周部にリング状の凸部が形成された半導体ウエハの凸部を研削する半導体ウエハの研削方法であって、半導体ウエハの外側で低くなるように砥石を斜めに傾けて凸部に当接させて、研削後の凸部のリング内側の高さと平坦部の高さとの差分が、研削時に発生する粒子の粒径以上となるように、凸部を斜めに研削する。【選択図】図7 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2022151258A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2022151258A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2022151258A3</originalsourceid><addsrcrecordid>eNrjZPD2dQ3x8HdRcPRzUXBxDfN0dlVw8w9ScA_y9HPx9HNXCHb19XT293MJdQ4BCoc7urkG6YAVY5HgYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkZGhqaGRqYWjsZEKQIAxWot4g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER</title><source>esp@cenet</source><creator>NUMAGUCHI HIROYUKI ; ICHIKI HIDEHIKO ; TAMEFUJI MITOKO ; KATO KAZUSUKE ; HISATOKU SHINJI ; SATO YOHEI ; DOI YUKI ; HIDAKA YU</creator><creatorcontrib>NUMAGUCHI HIROYUKI ; ICHIKI HIDEHIKO ; TAMEFUJI MITOKO ; KATO KAZUSUKE ; HISATOKU SHINJI ; SATO YOHEI ; DOI YUKI ; HIDAKA YU</creatorcontrib><description>To provide a method and device for grinding a semiconductor wafer and a semiconductor wafer, capable of suppressing the occurrence of scratches when a ring-shaped protrusion on the outer periphery of a semiconductor wafer is ground.SOLUTION: There is provided a method for grinding a semiconductor wafer for grinding a ring-shaped protrusion of a semiconductor wafer in which a flat part in a center on the rear face corresponding to a circuit formation area is thinned and the protrusion is formed on the outer periphery part on the rear face surrounding the flat part. In the method, a whetstone is tilted obliquely to be low on the outside of the semiconductor wafer to be brought into contact with the protrusion, and the protrusion is ground obliquely such that a difference between the height of the protrusion inside a ring after grinding and the height of the flat part is equal to or more than the particle diameter of particles generated during grinding.SELECTED DRAWING: Figure 7
【課題】半導体ウエハの外周部に在るリング状の凸部を研削する際に、スクラッチの発生を抑制することができる、半導体ウエハの研削方法、研削装置、及び半導体ウエハを提供する。【解決手段】回路形成領域に対応する裏面の中央の平坦部が薄化され、平坦部を取り囲む裏面の外周部にリング状の凸部が形成された半導体ウエハの凸部を研削する半導体ウエハの研削方法であって、半導体ウエハの外側で低くなるように砥石を斜めに傾けて凸部に当接させて、研削後の凸部のリング内側の高さと平坦部の高さとの差分が、研削時に発生する粒子の粒径以上となるように、凸部を斜めに研削する。【選択図】図7</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; DRESSING OR CONDITIONING OF ABRADING SURFACES ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS ; GRINDING ; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING ; PERFORMING OPERATIONS ; POLISHING ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221007&DB=EPODOC&CC=JP&NR=2022151258A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221007&DB=EPODOC&CC=JP&NR=2022151258A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NUMAGUCHI HIROYUKI</creatorcontrib><creatorcontrib>ICHIKI HIDEHIKO</creatorcontrib><creatorcontrib>TAMEFUJI MITOKO</creatorcontrib><creatorcontrib>KATO KAZUSUKE</creatorcontrib><creatorcontrib>HISATOKU SHINJI</creatorcontrib><creatorcontrib>SATO YOHEI</creatorcontrib><creatorcontrib>DOI YUKI</creatorcontrib><creatorcontrib>HIDAKA YU</creatorcontrib><title>METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER</title><description>To provide a method and device for grinding a semiconductor wafer and a semiconductor wafer, capable of suppressing the occurrence of scratches when a ring-shaped protrusion on the outer periphery of a semiconductor wafer is ground.SOLUTION: There is provided a method for grinding a semiconductor wafer for grinding a ring-shaped protrusion of a semiconductor wafer in which a flat part in a center on the rear face corresponding to a circuit formation area is thinned and the protrusion is formed on the outer periphery part on the rear face surrounding the flat part. In the method, a whetstone is tilted obliquely to be low on the outside of the semiconductor wafer to be brought into contact with the protrusion, and the protrusion is ground obliquely such that a difference between the height of the protrusion inside a ring after grinding and the height of the flat part is equal to or more than the particle diameter of particles generated during grinding.SELECTED DRAWING: Figure 7
【課題】半導体ウエハの外周部に在るリング状の凸部を研削する際に、スクラッチの発生を抑制することができる、半導体ウエハの研削方法、研削装置、及び半導体ウエハを提供する。【解決手段】回路形成領域に対応する裏面の中央の平坦部が薄化され、平坦部を取り囲む裏面の外周部にリング状の凸部が形成された半導体ウエハの凸部を研削する半導体ウエハの研削方法であって、半導体ウエハの外側で低くなるように砥石を斜めに傾けて凸部に当接させて、研削後の凸部のリング内側の高さと平坦部の高さとの差分が、研削時に発生する粒子の粒径以上となるように、凸部を斜めに研削する。【選択図】図7</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>DRESSING OR CONDITIONING OF ABRADING SURFACES</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</subject><subject>GRINDING</subject><subject>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</subject><subject>PERFORMING OPERATIONS</subject><subject>POLISHING</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPD2dQ3x8HdRcPRzUXBxDfN0dlVw8w9ScA_y9HPx9HNXCHb19XT293MJdQ4BCoc7urkG6YAVY5HgYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkZGhqaGRqYWjsZEKQIAxWot4g</recordid><startdate>20221007</startdate><enddate>20221007</enddate><creator>NUMAGUCHI HIROYUKI</creator><creator>ICHIKI HIDEHIKO</creator><creator>TAMEFUJI MITOKO</creator><creator>KATO KAZUSUKE</creator><creator>HISATOKU SHINJI</creator><creator>SATO YOHEI</creator><creator>DOI YUKI</creator><creator>HIDAKA YU</creator><scope>EVB</scope></search><sort><creationdate>20221007</creationdate><title>METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER</title><author>NUMAGUCHI HIROYUKI ; ICHIKI HIDEHIKO ; TAMEFUJI MITOKO ; KATO KAZUSUKE ; HISATOKU SHINJI ; SATO YOHEI ; DOI YUKI ; HIDAKA YU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2022151258A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>DRESSING OR CONDITIONING OF ABRADING SURFACES</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</topic><topic>GRINDING</topic><topic>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</topic><topic>PERFORMING OPERATIONS</topic><topic>POLISHING</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>NUMAGUCHI HIROYUKI</creatorcontrib><creatorcontrib>ICHIKI HIDEHIKO</creatorcontrib><creatorcontrib>TAMEFUJI MITOKO</creatorcontrib><creatorcontrib>KATO KAZUSUKE</creatorcontrib><creatorcontrib>HISATOKU SHINJI</creatorcontrib><creatorcontrib>SATO YOHEI</creatorcontrib><creatorcontrib>DOI YUKI</creatorcontrib><creatorcontrib>HIDAKA YU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NUMAGUCHI HIROYUKI</au><au>ICHIKI HIDEHIKO</au><au>TAMEFUJI MITOKO</au><au>KATO KAZUSUKE</au><au>HISATOKU SHINJI</au><au>SATO YOHEI</au><au>DOI YUKI</au><au>HIDAKA YU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER</title><date>2022-10-07</date><risdate>2022</risdate><abstract>To provide a method and device for grinding a semiconductor wafer and a semiconductor wafer, capable of suppressing the occurrence of scratches when a ring-shaped protrusion on the outer periphery of a semiconductor wafer is ground.SOLUTION: There is provided a method for grinding a semiconductor wafer for grinding a ring-shaped protrusion of a semiconductor wafer in which a flat part in a center on the rear face corresponding to a circuit formation area is thinned and the protrusion is formed on the outer periphery part on the rear face surrounding the flat part. In the method, a whetstone is tilted obliquely to be low on the outside of the semiconductor wafer to be brought into contact with the protrusion, and the protrusion is ground obliquely such that a difference between the height of the protrusion inside a ring after grinding and the height of the flat part is equal to or more than the particle diameter of particles generated during grinding.SELECTED DRAWING: Figure 7
【課題】半導体ウエハの外周部に在るリング状の凸部を研削する際に、スクラッチの発生を抑制することができる、半導体ウエハの研削方法、研削装置、及び半導体ウエハを提供する。【解決手段】回路形成領域に対応する裏面の中央の平坦部が薄化され、平坦部を取り囲む裏面の外周部にリング状の凸部が形成された半導体ウエハの凸部を研削する半導体ウエハの研削方法であって、半導体ウエハの外側で低くなるように砥石を斜めに傾けて凸部に当接させて、研削後の凸部のリング内側の高さと平坦部の高さとの差分が、研削時に発生する粒子の粒径以上となるように、凸部を斜めに研削する。【選択図】図7</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; jpn |
recordid | cdi_epo_espacenet_JP2022151258A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS DRESSING OR CONDITIONING OF ABRADING SURFACES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS GRINDING MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING PERFORMING OPERATIONS POLISHING SEMICONDUCTOR DEVICES TRANSPORTING |
title | METHOD AND DEVICE FOR GRINDING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T14%3A21%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NUMAGUCHI%20HIROYUKI&rft.date=2022-10-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2022151258A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |