NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS
To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side....
Gespeichert in:
| Hauptverfasser: | , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; jpn |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | AMOL D JADHAV WEI-LUN K JEN LEE KYU-OH GURUPRASAD ARAKERE KOUSIK GANESAN DEEPAK KULKARNI SAIRAM AGRAHARAM MANISH DUBEY NUMAIR AHMED |
| description | To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A
【課題】従来技術の問題を解決する。【解決手段】本明細書に開示する実施形態は、電子パッケージおよびそのような電子パッケージを形成する方法を含む。ある実施形態では、電子パッケージが、ダイ側とランド側とを有するパッケージ基板を含む。ある実施形態では、パッドが、ランド側の上にある。ある実施形態では、誘電体層が、パッドの側壁を覆い、表面仕上げが、パッドの露出表面の上にある。【選択図】図１Ａ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2022098442A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2022098442A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2022098442A3</originalsourceid><addsrcrecordid>eNqNyj0KwkAQQOE0FqLeYbAXwppCy3Ezm4zsH5M1YBWCrJVoIN4fLTyA1Su-tyzEh54s2AYBRbecSKeLEJggwC5K6Nk3IGQZT2w5XSGSfNGh1wTBgKOEFmoy7KmGiHW3Lhb38THnza-rYmso6XaXp9eQ52m85Wd-D-eoSqXK46GqFO7_mj4tPi_3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS</title><source>esp@cenet</source><creator>AMOL D JADHAV ; WEI-LUN K JEN ; LEE KYU-OH ; GURUPRASAD ARAKERE ; KOUSIK GANESAN ; DEEPAK KULKARNI ; SAIRAM AGRAHARAM ; MANISH DUBEY ; NUMAIR AHMED</creator><creatorcontrib>AMOL D JADHAV ; WEI-LUN K JEN ; LEE KYU-OH ; GURUPRASAD ARAKERE ; KOUSIK GANESAN ; DEEPAK KULKARNI ; SAIRAM AGRAHARAM ; MANISH DUBEY ; NUMAIR AHMED</creatorcontrib><description>To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A
【課題】従来技術の問題を解決する。【解決手段】本明細書に開示する実施形態は、電子パッケージおよびそのような電子パッケージを形成する方法を含む。ある実施形態では、電子パッケージが、ダイ側とランド側とを有するパッケージ基板を含む。ある実施形態では、パッドが、ランド側の上にある。ある実施形態では、誘電体層が、パッドの側壁を覆い、表面仕上げが、パッドの露出表面の上にある。【選択図】図１Ａ</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220701&DB=EPODOC&CC=JP&NR=2022098442A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220701&DB=EPODOC&CC=JP&NR=2022098442A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AMOL D JADHAV</creatorcontrib><creatorcontrib>WEI-LUN K JEN</creatorcontrib><creatorcontrib>LEE KYU-OH</creatorcontrib><creatorcontrib>GURUPRASAD ARAKERE</creatorcontrib><creatorcontrib>KOUSIK GANESAN</creatorcontrib><creatorcontrib>DEEPAK KULKARNI</creatorcontrib><creatorcontrib>SAIRAM AGRAHARAM</creatorcontrib><creatorcontrib>MANISH DUBEY</creatorcontrib><creatorcontrib>NUMAIR AHMED</creatorcontrib><title>NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS</title><description>To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A
【課題】従来技術の問題を解決する。【解決手段】本明細書に開示する実施形態は、電子パッケージおよびそのような電子パッケージを形成する方法を含む。ある実施形態では、電子パッケージが、ダイ側とランド側とを有するパッケージ基板を含む。ある実施形態では、パッドが、ランド側の上にある。ある実施形態では、誘電体層が、パッドの側壁を覆い、表面仕上げが、パッドの露出表面の上にある。【選択図】図１Ａ</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KwkAQQOE0FqLeYbAXwppCy3Ezm4zsH5M1YBWCrJVoIN4fLTyA1Su-tyzEh54s2AYBRbecSKeLEJggwC5K6Nk3IGQZT2w5XSGSfNGh1wTBgKOEFmoy7KmGiHW3Lhb38THnza-rYmso6XaXp9eQ52m85Wd-D-eoSqXK46GqFO7_mj4tPi_3</recordid><startdate>20220701</startdate><enddate>20220701</enddate><creator>AMOL D JADHAV</creator><creator>WEI-LUN K JEN</creator><creator>LEE KYU-OH</creator><creator>GURUPRASAD ARAKERE</creator><creator>KOUSIK GANESAN</creator><creator>DEEPAK KULKARNI</creator><creator>SAIRAM AGRAHARAM</creator><creator>MANISH DUBEY</creator><creator>NUMAIR AHMED</creator><scope>EVB</scope></search><sort><creationdate>20220701</creationdate><title>NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS</title><author>AMOL D JADHAV ; WEI-LUN K JEN ; LEE KYU-OH ; GURUPRASAD ARAKERE ; KOUSIK GANESAN ; DEEPAK KULKARNI ; SAIRAM AGRAHARAM ; MANISH DUBEY ; NUMAIR AHMED</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2022098442A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AMOL D JADHAV</creatorcontrib><creatorcontrib>WEI-LUN K JEN</creatorcontrib><creatorcontrib>LEE KYU-OH</creatorcontrib><creatorcontrib>GURUPRASAD ARAKERE</creatorcontrib><creatorcontrib>KOUSIK GANESAN</creatorcontrib><creatorcontrib>DEEPAK KULKARNI</creatorcontrib><creatorcontrib>SAIRAM AGRAHARAM</creatorcontrib><creatorcontrib>MANISH DUBEY</creatorcontrib><creatorcontrib>NUMAIR AHMED</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AMOL D JADHAV</au><au>WEI-LUN K JEN</au><au>LEE KYU-OH</au><au>GURUPRASAD ARAKERE</au><au>KOUSIK GANESAN</au><au>DEEPAK KULKARNI</au><au>SAIRAM AGRAHARAM</au><au>MANISH DUBEY</au><au>NUMAIR AHMED</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS</title><date>2022-07-01</date><risdate>2022</risdate><abstract>To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A
【課題】従来技術の問題を解決する。【解決手段】本明細書に開示する実施形態は、電子パッケージおよびそのような電子パッケージを形成する方法を含む。ある実施形態では、電子パッケージが、ダイ側とランド側とを有するパッケージ基板を含む。ある実施形態では、パッドが、ランド側の上にある。ある実施形態では、誘電体層が、パッドの側壁を覆い、表面仕上げが、パッドの露出表面の上にある。【選択図】図１Ａ</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; jpn |
| recordid | cdi_epo_espacenet_JP2022098442A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T11%3A07%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AMOL%20D%20JADHAV&rft.date=2022-07-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2022098442A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |