OPERATION DEVICE AND METHOD FOR TEST
To reduce the time for a test.SOLUTION: An operation device runs a test by using a re-reconfigurable programmable logic part. The programmable logic part has a test target circuit as a user circuit and a non-test circuit as a user circuit which is not a test target circuit. The operation device incl...
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| creator | SHINPO KENICHI TOBA TADANOBU YAMASHITA TAKEO NONAKA SHINICHI ARATA SUMIYUKI IKEDA YASUHIRO ICHIGE ATSUSHI |
| description | To reduce the time for a test.SOLUTION: An operation device runs a test by using a re-reconfigurable programmable logic part. The programmable logic part has a test target circuit as a user circuit and a non-test circuit as a user circuit which is not a test target circuit. The operation device includes: a configure control unit for forming a test partition unit for separating the test target circuit and the non-test target circuit in the programmable logic part by a partial reconfiguration; and a partition control unit for controlling the test partition unit for running a test on the test target circuit.SELECTED DRAWING: Figure 1
【課題】テスト時間を短縮できる。【解決手段】演算装置は、部分再構成可能なプログラマブルロジック部を用いてテストを実行し、プログラマブルロジック部には、ユーザ回路であるテスト対象回路およびテスト対象回路ではないユーザ回路である非テスト回路が構成され、テスト対象回路と非テスト回路とを分離するテストパーテーション部を部分再構成によりプログラマブルロジック部に形成させるコンフィグ制御部と、テスト対象回路のテストを行うためにテストパーテーション部を制御するパーテーション制御部とを備える。【選択図】図１ |
| format | Patent |
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【課題】テスト時間を短縮できる。【解決手段】演算装置は、部分再構成可能なプログラマブルロジック部を用いてテストを実行し、プログラマブルロジック部には、ユーザ回路であるテスト対象回路およびテスト対象回路ではないユーザ回路である非テスト回路が構成され、テスト対象回路と非テスト回路とを分離するテストパーテーション部を部分再構成によりプログラマブルロジック部に形成させるコンフィグ制御部と、テスト対象回路のテストを行うためにテストパーテーション部を制御するパーテーション制御部とを備える。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220525&DB=EPODOC&CC=JP&NR=2022078892A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220525&DB=EPODOC&CC=JP&NR=2022078892A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHINPO KENICHI</creatorcontrib><creatorcontrib>TOBA TADANOBU</creatorcontrib><creatorcontrib>YAMASHITA TAKEO</creatorcontrib><creatorcontrib>NONAKA SHINICHI</creatorcontrib><creatorcontrib>ARATA SUMIYUKI</creatorcontrib><creatorcontrib>IKEDA YASUHIRO</creatorcontrib><creatorcontrib>ICHIGE ATSUSHI</creatorcontrib><title>OPERATION DEVICE AND METHOD FOR TEST</title><description>To reduce the time for a test.SOLUTION: An operation device runs a test by using a re-reconfigurable programmable logic part. The programmable logic part has a test target circuit as a user circuit and a non-test circuit as a user circuit which is not a test target circuit. The operation device includes: a configure control unit for forming a test partition unit for separating the test target circuit and the non-test target circuit in the programmable logic part by a partial reconfiguration; and a partition control unit for controlling the test partition unit for running a test on the test target circuit.SELECTED DRAWING: Figure 1
【課題】テスト時間を短縮できる。【解決手段】演算装置は、部分再構成可能なプログラマブルロジック部を用いてテストを実行し、プログラマブルロジック部には、ユーザ回路であるテスト対象回路およびテスト対象回路ではないユーザ回路である非テスト回路が構成され、テスト対象回路と非テスト回路とを分離するテストパーテーション部を部分再構成によりプログラマブルロジック部に形成させるコンフィグ制御部と、テスト対象回路のテストを行うためにテストパーテーション部を制御するパーテーション制御部とを備える。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDxD3ANcgzx9PdTcHEN83R2VXD0c1HwdQ3x8HdRcPMPUghxDQ7hYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkZGBuYWFpZGjsZEKQIArk0jSw</recordid><startdate>20220525</startdate><enddate>20220525</enddate><creator>SHINPO KENICHI</creator><creator>TOBA TADANOBU</creator><creator>YAMASHITA TAKEO</creator><creator>NONAKA SHINICHI</creator><creator>ARATA SUMIYUKI</creator><creator>IKEDA YASUHIRO</creator><creator>ICHIGE ATSUSHI</creator><scope>EVB</scope></search><sort><creationdate>20220525</creationdate><title>OPERATION DEVICE AND METHOD FOR TEST</title><author>SHINPO KENICHI ; TOBA TADANOBU ; YAMASHITA TAKEO ; NONAKA SHINICHI ; ARATA SUMIYUKI ; IKEDA YASUHIRO ; ICHIGE ATSUSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2022078892A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>SHINPO KENICHI</creatorcontrib><creatorcontrib>TOBA TADANOBU</creatorcontrib><creatorcontrib>YAMASHITA TAKEO</creatorcontrib><creatorcontrib>NONAKA SHINICHI</creatorcontrib><creatorcontrib>ARATA SUMIYUKI</creatorcontrib><creatorcontrib>IKEDA YASUHIRO</creatorcontrib><creatorcontrib>ICHIGE ATSUSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHINPO KENICHI</au><au>TOBA TADANOBU</au><au>YAMASHITA TAKEO</au><au>NONAKA SHINICHI</au><au>ARATA SUMIYUKI</au><au>IKEDA YASUHIRO</au><au>ICHIGE ATSUSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>OPERATION DEVICE AND METHOD FOR TEST</title><date>2022-05-25</date><risdate>2022</risdate><abstract>To reduce the time for a test.SOLUTION: An operation device runs a test by using a re-reconfigurable programmable logic part. The programmable logic part has a test target circuit as a user circuit and a non-test circuit as a user circuit which is not a test target circuit. The operation device includes: a configure control unit for forming a test partition unit for separating the test target circuit and the non-test target circuit in the programmable logic part by a partial reconfiguration; and a partition control unit for controlling the test partition unit for running a test on the test target circuit.SELECTED DRAWING: Figure 1
【課題】テスト時間を短縮できる。【解決手段】演算装置は、部分再構成可能なプログラマブルロジック部を用いてテストを実行し、プログラマブルロジック部には、ユーザ回路であるテスト対象回路およびテスト対象回路ではないユーザ回路である非テスト回路が構成され、テスト対象回路と非テスト回路とを分離するテストパーテーション部を部分再構成によりプログラマブルロジック部に形成させるコンフィグ制御部と、テスト対象回路のテストを行うためにテストパーテーション部を制御するパーテーション制御部とを備える。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | OPERATION DEVICE AND METHOD FOR TEST |
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