TRANSISTOR GATE STRUCTURE AND FORMING METHOD

To provide a device and a method for integrating more components into a predetermined area by reducing the minimum feature amount.SOLUTION: A nanostructure transistor/FET includes a separation area 72, a nanostructure 66 projecting above the top surface of the separation area, a gate structure 130 i...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LIN CHIH-HAN, LEE HSIAOWEN, RIN SHIGYO, CHEN CHEN-PING
Format:	Patent
Sprache:	eng ; jpn
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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