CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD
To provide a chip component mounting method that can apply solder to second chip components that are stacked in multiple layers on a first chip component on a printed circuit board.SOLUTION: A solder 23 is applied to second component pads 20, which are formed on a printed circuit board 10 and to whi...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; jpn |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | NAGAMINE TAKAHIRO KASHIMA MASANORI SHIBATA YOSHIHIRO |
| description | To provide a chip component mounting method that can apply solder to second chip components that are stacked in multiple layers on a first chip component on a printed circuit board.SOLUTION: A solder 23 is applied to second component pads 20, which are formed on a printed circuit board 10 and to which second chip components 12, which are stacked in multiple layers with respect to the first chip component 11 mounted on first component pads 30 formed on the printed circuit board 10, are mounted. The second chip component 12 is mounted on the solder 23 applied to the second component pads 20. The second chip components 12 are detached from the second component pads 20. The second chip components 12 are mounted on the first component pads 30.SELECTED DRAWING: Figure 5
【課題】プリント基板上において、第１チップ部品に多段積みされる第２チップ部品に対して、はんだを塗布することができるチップ部品の実装方法を提供する。【解決手段】プリント基板１０上に形成され、当該プリント基板１０上に形成された第１部品パッド３０に装着される第１チップ部品１１に対して多段積みされる第２チップ部品１２が装着される第２部品パッド２０に、はんだ２３を塗布し、第２部品パッド２０に塗布されたはんだ２３上に、第２チップ部品１２を装着し、第２チップ部品１２を第２部品パッド２０から切り離し、第２チップ部品１２を第１部品パッド３０上に装着する。【選択図】図５ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2021141296A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2021141296A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2021141296A3</originalsourceid><addsrcrecordid>eNrjZLBw9vAMUHD29w3w93P1C1Hw9Q_1C_H0c1fwdQ3x8HdRcPRzUQgI8vQLcXVRcPYMcg71DFFw8ncMcuFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRoaGJoZGlmaOxkQpAgCxcSjY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD</title><source>esp@cenet</source><creator>NAGAMINE TAKAHIRO ; KASHIMA MASANORI ; SHIBATA YOSHIHIRO</creator><creatorcontrib>NAGAMINE TAKAHIRO ; KASHIMA MASANORI ; SHIBATA YOSHIHIRO</creatorcontrib><description>To provide a chip component mounting method that can apply solder to second chip components that are stacked in multiple layers on a first chip component on a printed circuit board.SOLUTION: A solder 23 is applied to second component pads 20, which are formed on a printed circuit board 10 and to which second chip components 12, which are stacked in multiple layers with respect to the first chip component 11 mounted on first component pads 30 formed on the printed circuit board 10, are mounted. The second chip component 12 is mounted on the solder 23 applied to the second component pads 20. The second chip components 12 are detached from the second component pads 20. The second chip components 12 are mounted on the first component pads 30.SELECTED DRAWING: Figure 5
【課題】プリント基板上において、第１チップ部品に多段積みされる第２チップ部品に対して、はんだを塗布することができるチップ部品の実装方法を提供する。【解決手段】プリント基板１０上に形成され、当該プリント基板１０上に形成された第１部品パッド３０に装着される第１チップ部品１１に対して多段積みされる第２チップ部品１２が装着される第２部品パッド２０に、はんだ２３を塗布し、第２部品パッド２０に塗布されたはんだ２３上に、第２チップ部品１２を装着し、第２チップ部品１２を第２部品パッド２０から切り離し、第２チップ部品１２を第１部品パッド３０上に装着する。【選択図】図５</description><language>eng ; jpn</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210916&DB=EPODOC&CC=JP&NR=2021141296A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210916&DB=EPODOC&CC=JP&NR=2021141296A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAGAMINE TAKAHIRO</creatorcontrib><creatorcontrib>KASHIMA MASANORI</creatorcontrib><creatorcontrib>SHIBATA YOSHIHIRO</creatorcontrib><title>CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD</title><description>To provide a chip component mounting method that can apply solder to second chip components that are stacked in multiple layers on a first chip component on a printed circuit board.SOLUTION: A solder 23 is applied to second component pads 20, which are formed on a printed circuit board 10 and to which second chip components 12, which are stacked in multiple layers with respect to the first chip component 11 mounted on first component pads 30 formed on the printed circuit board 10, are mounted. The second chip component 12 is mounted on the solder 23 applied to the second component pads 20. The second chip components 12 are detached from the second component pads 20. The second chip components 12 are mounted on the first component pads 30.SELECTED DRAWING: Figure 5
【課題】プリント基板上において、第１チップ部品に多段積みされる第２チップ部品に対して、はんだを塗布することができるチップ部品の実装方法を提供する。【解決手段】プリント基板１０上に形成され、当該プリント基板１０上に形成された第１部品パッド３０に装着される第１チップ部品１１に対して多段積みされる第２チップ部品１２が装着される第２部品パッド２０に、はんだ２３を塗布し、第２部品パッド２０に塗布されたはんだ２３上に、第２チップ部品１２を装着し、第２チップ部品１２を第２部品パッド２０から切り離し、第２チップ部品１２を第１部品パッド３０上に装着する。【選択図】図５</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBw9vAMUHD29w3w93P1C1Hw9Q_1C_H0c1fwdQ3x8HdRcPRzUQgI8vQLcXVRcPYMcg71DFFw8ncMcuFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRoaGJoZGlmaOxkQpAgCxcSjY</recordid><startdate>20210916</startdate><enddate>20210916</enddate><creator>NAGAMINE TAKAHIRO</creator><creator>KASHIMA MASANORI</creator><creator>SHIBATA YOSHIHIRO</creator><scope>EVB</scope></search><sort><creationdate>20210916</creationdate><title>CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD</title><author>NAGAMINE TAKAHIRO ; KASHIMA MASANORI ; SHIBATA YOSHIHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2021141296A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2021</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>NAGAMINE TAKAHIRO</creatorcontrib><creatorcontrib>KASHIMA MASANORI</creatorcontrib><creatorcontrib>SHIBATA YOSHIHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAGAMINE TAKAHIRO</au><au>KASHIMA MASANORI</au><au>SHIBATA YOSHIHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD</title><date>2021-09-16</date><risdate>2021</risdate><abstract>To provide a chip component mounting method that can apply solder to second chip components that are stacked in multiple layers on a first chip component on a printed circuit board.SOLUTION: A solder 23 is applied to second component pads 20, which are formed on a printed circuit board 10 and to which second chip components 12, which are stacked in multiple layers with respect to the first chip component 11 mounted on first component pads 30 formed on the printed circuit board 10, are mounted. The second chip component 12 is mounted on the solder 23 applied to the second component pads 20. The second chip components 12 are detached from the second component pads 20. The second chip components 12 are mounted on the first component pads 30.SELECTED DRAWING: Figure 5
【課題】プリント基板上において、第１チップ部品に多段積みされる第２チップ部品に対して、はんだを塗布することができるチップ部品の実装方法を提供する。【解決手段】プリント基板１０上に形成され、当該プリント基板１０上に形成された第１部品パッド３０に装着される第１チップ部品１１に対して多段積みされる第２チップ部品１２が装着される第２部品パッド２０に、はんだ２３を塗布し、第２部品パッド２０に塗布されたはんだ２３上に、第２チップ部品１２を装着し、第２チップ部品１２を第２部品パッド２０から切り離し、第２チップ部品１２を第１部品パッド３０上に装着する。【選択図】図５</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; jpn |
| recordid | cdi_epo_espacenet_JP2021141296A |
| source | esp@cenet |
| subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
| title | CHIP COMPONENT MOUNTING METHOD AND PRINTED CIRCUIT BOARD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T01%3A24%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAGAMINE%20TAKAHIRO&rft.date=2021-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2021141296A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |