FLASH MEMORY SYSTEM
To reduce start-up time while reliably starting a flash memory system.SOLUTION: A flash memory system 1 includes a memory controller 20, a flash memory 10, a power supply circuit 30, and a control circuit 40. The power supply circuit 30 includes: a power terminal 31 to which external power is suppli...
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| creator | ITO SUKEYOSHI OKAKO NORIKAZU |
| description | To reduce start-up time while reliably starting a flash memory system.SOLUTION: A flash memory system 1 includes a memory controller 20, a flash memory 10, a power supply circuit 30, and a control circuit 40. The power supply circuit 30 includes: a power terminal 31 to which external power is supplied; a booster circuit 32 which generates a second voltage V2 higher than a first voltage V1 by increasing the first voltage V1 based on the external power; a capacitor C to be charged with the second voltage V2; and step-down circuits 34a, 34b which generate a third voltage V3 lower than the second voltage V2 by reducing the second voltage V2, to be supplied to the flash memory 10 as an operating voltage. The control circuit 40 includes: a circuit for controlling active state/inactive state of the flash memory 10 on the basis of the voltage value of the third voltage V3; and a circuit for controlling active state/inactive state of the memory controller 20 on the basis of voltage values of a voltage of the external power and the third voltage V3.SELECTED DRAWING: Figure 1
【課題】フラッシュメモリシステムの起動を確実としつつ起動時間の短縮を図る。【解決手段】フラッシュメモリシステム１は、メモリコントローラ２０、フラッシュメモリ１０、電源回路３０、制御回路４０を備える。電源回路３０は、外部電源が供給される電源端子３１、外部電源に基づいた第１の電圧Ｖ１を昇圧することによって第１の電圧Ｖ１よりも高い第２の電圧Ｖ２を生成する昇圧回路３２、第２の電圧Ｖ２によって充電されるキャパシタＣ、第２の電圧Ｖ２を降圧することによって第２の電圧Ｖ２よりも低い第３の電圧Ｖ３を生成し動作電圧としてフラッシュメモリ１０に供給する降圧回路３４ａ、３４ｂを含む。制御回路４０は、第３の電圧Ｖ３の電圧値に基づいてフラッシュメモリ１０の活性状態又は非活性状態を制御する回路、外部電源の電圧及び第３の電圧Ｖ３の双方の電圧値に基づいてメモリコントローラ２０の活性状態又は非活性状態を制御する回路を含む。【選択図】図１ |
| format | Patent |
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【課題】フラッシュメモリシステムの起動を確実としつつ起動時間の短縮を図る。【解決手段】フラッシュメモリシステム１は、メモリコントローラ２０、フラッシュメモリ１０、電源回路３０、制御回路４０を備える。電源回路３０は、外部電源が供給される電源端子３１、外部電源に基づいた第１の電圧Ｖ１を昇圧することによって第１の電圧Ｖ１よりも高い第２の電圧Ｖ２を生成する昇圧回路３２、第２の電圧Ｖ２によって充電されるキャパシタＣ、第２の電圧Ｖ２を降圧することによって第２の電圧Ｖ２よりも低い第３の電圧Ｖ３を生成し動作電圧としてフラッシュメモリ１０に供給する降圧回路３４ａ、３４ｂを含む。制御回路４０は、第３の電圧Ｖ３の電圧値に基づいてフラッシュメモリ１０の活性状態又は非活性状態を制御する回路、外部電源の電圧及び第３の電圧Ｖ３の双方の電圧値に基づいてメモリコントローラ２０の活性状態又は非活性状態を制御する回路を含む。【選択図】図１</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210527&DB=EPODOC&CC=JP&NR=2021082100A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210527&DB=EPODOC&CC=JP&NR=2021082100A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ITO SUKEYOSHI</creatorcontrib><creatorcontrib>OKAKO NORIKAZU</creatorcontrib><title>FLASH MEMORY SYSTEM</title><description>To reduce start-up time while reliably starting a flash memory system.SOLUTION: A flash memory system 1 includes a memory controller 20, a flash memory 10, a power supply circuit 30, and a control circuit 40. The power supply circuit 30 includes: a power terminal 31 to which external power is supplied; a booster circuit 32 which generates a second voltage V2 higher than a first voltage V1 by increasing the first voltage V1 based on the external power; a capacitor C to be charged with the second voltage V2; and step-down circuits 34a, 34b which generate a third voltage V3 lower than the second voltage V2 by reducing the second voltage V2, to be supplied to the flash memory 10 as an operating voltage. The control circuit 40 includes: a circuit for controlling active state/inactive state of the flash memory 10 on the basis of the voltage value of the third voltage V3; and a circuit for controlling active state/inactive state of the memory controller 20 on the basis of voltage values of a voltage of the external power and the third voltage V3.SELECTED DRAWING: Figure 1
【課題】フラッシュメモリシステムの起動を確実としつつ起動時間の短縮を図る。【解決手段】フラッシュメモリシステム１は、メモリコントローラ２０、フラッシュメモリ１０、電源回路３０、制御回路４０を備える。電源回路３０は、外部電源が供給される電源端子３１、外部電源に基づいた第１の電圧Ｖ１を昇圧することによって第１の電圧Ｖ１よりも高い第２の電圧Ｖ２を生成する昇圧回路３２、第２の電圧Ｖ２によって充電されるキャパシタＣ、第２の電圧Ｖ２を降圧することによって第２の電圧Ｖ２よりも低い第３の電圧Ｖ３を生成し動作電圧としてフラッシュメモリ１０に供給する降圧回路３４ａ、３４ｂを含む。制御回路４０は、第３の電圧Ｖ３の電圧値に基づいてフラッシュメモリ１０の活性状態又は非活性状態を制御する回路、外部電源の電圧及び第３の電圧Ｖ３の双方の電圧値に基づいてメモリコントローラ２０の活性状態又は非活性状態を制御する回路を含む。【選択図】図１</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB283EM9lDwdfX1D4pUCI4MDnH15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgZGhgYWQGzgaEyUIgCaox66</recordid><startdate>20210527</startdate><enddate>20210527</enddate><creator>ITO SUKEYOSHI</creator><creator>OKAKO NORIKAZU</creator><scope>EVB</scope></search><sort><creationdate>20210527</creationdate><title>FLASH MEMORY SYSTEM</title><author>ITO SUKEYOSHI ; OKAKO NORIKAZU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2021082100A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ITO SUKEYOSHI</creatorcontrib><creatorcontrib>OKAKO NORIKAZU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ITO SUKEYOSHI</au><au>OKAKO NORIKAZU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FLASH MEMORY SYSTEM</title><date>2021-05-27</date><risdate>2021</risdate><abstract>To reduce start-up time while reliably starting a flash memory system.SOLUTION: A flash memory system 1 includes a memory controller 20, a flash memory 10, a power supply circuit 30, and a control circuit 40. The power supply circuit 30 includes: a power terminal 31 to which external power is supplied; a booster circuit 32 which generates a second voltage V2 higher than a first voltage V1 by increasing the first voltage V1 based on the external power; a capacitor C to be charged with the second voltage V2; and step-down circuits 34a, 34b which generate a third voltage V3 lower than the second voltage V2 by reducing the second voltage V2, to be supplied to the flash memory 10 as an operating voltage. The control circuit 40 includes: a circuit for controlling active state/inactive state of the flash memory 10 on the basis of the voltage value of the third voltage V3; and a circuit for controlling active state/inactive state of the memory controller 20 on the basis of voltage values of a voltage of the external power and the third voltage V3.SELECTED DRAWING: Figure 1
【課題】フラッシュメモリシステムの起動を確実としつつ起動時間の短縮を図る。【解決手段】フラッシュメモリシステム１は、メモリコントローラ２０、フラッシュメモリ１０、電源回路３０、制御回路４０を備える。電源回路３０は、外部電源が供給される電源端子３１、外部電源に基づいた第１の電圧Ｖ１を昇圧することによって第１の電圧Ｖ１よりも高い第２の電圧Ｖ２を生成する昇圧回路３２、第２の電圧Ｖ２によって充電されるキャパシタＣ、第２の電圧Ｖ２を降圧することによって第２の電圧Ｖ２よりも低い第３の電圧Ｖ３を生成し動作電圧としてフラッシュメモリ１０に供給する降圧回路３４ａ、３４ｂを含む。制御回路４０は、第３の電圧Ｖ３の電圧値に基づいてフラッシュメモリ１０の活性状態又は非活性状態を制御する回路、外部電源の電圧及び第３の電圧Ｖ３の双方の電圧値に基づいてメモリコントローラ２０の活性状態又は非活性状態を制御する回路を含む。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | FLASH MEMORY SYSTEM |
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