SEMICONDUCTOR DEVICE AND APPARATUS
To provide a technique that is advantageous for improving the stability of a memory cell and increasing the operating speed in a semiconductor device.SOLUTION: The semiconductor device including a memory cell having a holding node for holding a signal includes the first conductive pattern that const...
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| creator | KATO TATSUNORI TSURU HIROMU ISHII RYUNOSUKE OSETO AKIRA |
| description | To provide a technique that is advantageous for improving the stability of a memory cell and increasing the operating speed in a semiconductor device.SOLUTION: The semiconductor device including a memory cell having a holding node for holding a signal includes the first conductive pattern that constitutes the holding node, the second conductive pattern that is capacitively coupled to the first conductive pattern, a potential supply unit that supplies potential to the second conductive pattern, and a switch for controlling the connection state between the second conductive pattern and the potential supply unit.SELECTED DRAWING: Figure 1
【課題】半導体装置において、メモリセルの安定性の向上および動作速度の高速化に有利な技術を提供する。【解決手段】信号を保持する保持ノードを有するメモリセルを含む半導体装置であって、保持ノードを構成する第１導電パターンと、第１導電パターンに容量結合した第２導電パターンと、第２導電パターンに電位を供給する電位供給部と、第２導電パターンと電位供給部との間の接続状態を制御するスイッチと、を備える。【選択図】図１ |
| format | Patent |
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【課題】半導体装置において、メモリセルの安定性の向上および動作速度の高速化に有利な技術を提供する。【解決手段】信号を保持する保持ノードを有するメモリセルを含む半導体装置であって、保持ノードを構成する第１導電パターンと、第１導電パターンに容量結合した第２導電パターンと、第２導電パターンに電位を供給する電位供給部と、第２導電パターンと電位供給部との間の接続状態を制御するスイッチと、を備える。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210415&DB=EPODOC&CC=JP&NR=2021061350A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210415&DB=EPODOC&CC=JP&NR=2021061350A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KATO TATSUNORI</creatorcontrib><creatorcontrib>TSURU HIROMU</creatorcontrib><creatorcontrib>ISHII RYUNOSUKE</creatorcontrib><creatorcontrib>OSETO AKIRA</creatorcontrib><title>SEMICONDUCTOR DEVICE AND APPARATUS</title><description>To provide a technique that is advantageous for improving the stability of a memory cell and increasing the operating speed in a semiconductor device.SOLUTION: The semiconductor device including a memory cell having a holding node for holding a signal includes the first conductive pattern that constitutes the holding node, the second conductive pattern that is capacitively coupled to the first conductive pattern, a potential supply unit that supplies potential to the second conductive pattern, and a switch for controlling the connection state between the second conductive pattern and the potential supply unit.SELECTED DRAWING: Figure 1
【課題】半導体装置において、メモリセルの安定性の向上および動作速度の高速化に有利な技術を提供する。【解決手段】信号を保持する保持ノードを有するメモリセルを含む半導体装置であって、保持ノードを構成する第１導電パターンと、第１導電パターンに容量結合した第２導電パターンと、第２導電パターンに電位を供給する電位供給部と、第２導電パターンと電位供給部との間の接続状態を制御するスイッチと、を備える。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRcAwIcAxyDAkN5mFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgZGhgZmhsamBo7GRCkCAIA7Itg</recordid><startdate>20210415</startdate><enddate>20210415</enddate><creator>KATO TATSUNORI</creator><creator>TSURU HIROMU</creator><creator>ISHII RYUNOSUKE</creator><creator>OSETO AKIRA</creator><scope>EVB</scope></search><sort><creationdate>20210415</creationdate><title>SEMICONDUCTOR DEVICE AND APPARATUS</title><author>KATO TATSUNORI ; TSURU HIROMU ; ISHII RYUNOSUKE ; OSETO AKIRA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2021061350A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KATO TATSUNORI</creatorcontrib><creatorcontrib>TSURU HIROMU</creatorcontrib><creatorcontrib>ISHII RYUNOSUKE</creatorcontrib><creatorcontrib>OSETO AKIRA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KATO TATSUNORI</au><au>TSURU HIROMU</au><au>ISHII RYUNOSUKE</au><au>OSETO AKIRA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND APPARATUS</title><date>2021-04-15</date><risdate>2021</risdate><abstract>To provide a technique that is advantageous for improving the stability of a memory cell and increasing the operating speed in a semiconductor device.SOLUTION: The semiconductor device including a memory cell having a holding node for holding a signal includes the first conductive pattern that constitutes the holding node, the second conductive pattern that is capacitively coupled to the first conductive pattern, a potential supply unit that supplies potential to the second conductive pattern, and a switch for controlling the connection state between the second conductive pattern and the potential supply unit.SELECTED DRAWING: Figure 1
【課題】半導体装置において、メモリセルの安定性の向上および動作速度の高速化に有利な技術を提供する。【解決手段】信号を保持する保持ノードを有するメモリセルを含む半導体装置であって、保持ノードを構成する第１導電パターンと、第１導電パターンに容量結合した第２導電パターンと、第２導電パターンに電位を供給する電位供給部と、第２導電パターンと電位供給部との間の接続状態を制御するスイッチと、を備える。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | SEMICONDUCTOR DEVICE AND APPARATUS |
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