SEMICONDUCTOR STORAGE DEVICE
To provide a semiconductor storage device capable of performing high-speed operation.SOLUTION: A semiconductor storage device 1 of an embodiment includes a block BLK0 having a plurality of memory cells, a block BLK1 having a plurality of memory cells, and a control circuit configured to subsequently...
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| creator | YAMAOKA MASASHI |
| description | To provide a semiconductor storage device capable of performing high-speed operation.SOLUTION: A semiconductor storage device 1 of an embodiment includes a block BLK0 having a plurality of memory cells, a block BLK1 having a plurality of memory cells, and a control circuit configured to subsequently apply a second voltage VREAD greater than a first voltage VSS after applying the first voltage to a first memory cell in the block BLK0 or BLK1, and then apply a third voltage VCGRV after applying the second voltage. When the first memory cell is included in the block BLK0, the control circuit is configured to apply the third voltage to the first memory cell at a timing which is earlier by a first time ΔT11 than a time from applying the second voltage when the first memory cell is included in the block BLK1.SELECTED DRAWING: Figure 11
【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置１は、複数のメモリセルを含むブロックＢＬＫ０と、複数のメモリセルを含むブロックＢＬＫ１と、ブロックＢＬＫ０またはブロックＢＬＫ１の第１メモリセルに、第１電圧ＶＳＳを印加した後に前記第１電圧より大きい第２電圧ＶＲＥＡＤを続けて印加し、前記第２電圧を印加した後に第３電圧ＶＣＧＲＶを印加するように構成される制御回路とを含み、前記制御回路は、前記第１メモリセルがブロックＢＬＫ０に含まれる場合、前記第１メモリセルがブロックＢＬＫ１に含まれる場合よりも、前記第２電圧を印加してからの時間が第１時間ΔＴ１１だけ早いタイミングで、前記第１メモリセルに前記第３電圧を印加するように構成される。【選択図】図１１ |
| format | Patent |
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【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置１は、複数のメモリセルを含むブロックＢＬＫ０と、複数のメモリセルを含むブロックＢＬＫ１と、ブロックＢＬＫ０またはブロックＢＬＫ１の第１メモリセルに、第１電圧ＶＳＳを印加した後に前記第１電圧より大きい第２電圧ＶＲＥＡＤを続けて印加し、前記第２電圧を印加した後に第３電圧ＶＣＧＲＶを印加するように構成される制御回路とを含み、前記制御回路は、前記第１メモリセルがブロックＢＬＫ０に含まれる場合、前記第１メモリセルがブロックＢＬＫ１に含まれる場合よりも、前記第２電圧を印加してからの時間が第１時間ΔＴ１１だけ早いタイミングで、前記第１メモリセルに前記第３電圧を印加するように構成される。【選択図】図１１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200924&DB=EPODOC&CC=JP&NR=2020155184A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200924&DB=EPODOC&CC=JP&NR=2020155184A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAOKA MASASHI</creatorcontrib><title>SEMICONDUCTOR STORAGE DEVICE</title><description>To provide a semiconductor storage device capable of performing high-speed operation.SOLUTION: A semiconductor storage device 1 of an embodiment includes a block BLK0 having a plurality of memory cells, a block BLK1 having a plurality of memory cells, and a control circuit configured to subsequently apply a second voltage VREAD greater than a first voltage VSS after applying the first voltage to a first memory cell in the block BLK0 or BLK1, and then apply a third voltage VCGRV after applying the second voltage. When the first memory cell is included in the block BLK0, the control circuit is configured to apply the third voltage to the first memory cell at a timing which is earlier by a first time ΔT11 than a time from applying the second voltage when the first memory cell is included in the block BLK1.SELECTED DRAWING: Figure 11
【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置１は、複数のメモリセルを含むブロックＢＬＫ０と、複数のメモリセルを含むブロックＢＬＫ１と、ブロックＢＬＫ０またはブロックＢＬＫ１の第１メモリセルに、第１電圧ＶＳＳを印加した後に前記第１電圧より大きい第２電圧ＶＲＥＡＤを続けて印加し、前記第２電圧を印加した後に第３電圧ＶＣＧＲＶを印加するように構成される制御回路とを含み、前記制御回路は、前記第１メモリセルがブロックＢＬＫ０に含まれる場合、前記第１メモリセルがブロックＢＬＫ１に含まれる場合よりも、前記第２電圧を印加してからの時間が第１時間ΔＴ１１だけ早いタイミングで、前記第１メモリセルに前記第３電圧を印加するように構成される。【選択図】図１１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAJdvX1dPb3cwl1DvEPUggGEo7urgourmGezq48DKxpiTnFqbxQmptByc01xNlDN7UgPz61uCAxOTUvtSTeK8DIwMjA0NTU0MLE0ZgoRQDAACFT</recordid><startdate>20200924</startdate><enddate>20200924</enddate><creator>YAMAOKA MASASHI</creator><scope>EVB</scope></search><sort><creationdate>20200924</creationdate><title>SEMICONDUCTOR STORAGE DEVICE</title><author>YAMAOKA MASASHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2020155184A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAOKA MASASHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAOKA MASASHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR STORAGE DEVICE</title><date>2020-09-24</date><risdate>2020</risdate><abstract>To provide a semiconductor storage device capable of performing high-speed operation.SOLUTION: A semiconductor storage device 1 of an embodiment includes a block BLK0 having a plurality of memory cells, a block BLK1 having a plurality of memory cells, and a control circuit configured to subsequently apply a second voltage VREAD greater than a first voltage VSS after applying the first voltage to a first memory cell in the block BLK0 or BLK1, and then apply a third voltage VCGRV after applying the second voltage. When the first memory cell is included in the block BLK0, the control circuit is configured to apply the third voltage to the first memory cell at a timing which is earlier by a first time ΔT11 than a time from applying the second voltage when the first memory cell is included in the block BLK1.SELECTED DRAWING: Figure 11
【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置１は、複数のメモリセルを含むブロックＢＬＫ０と、複数のメモリセルを含むブロックＢＬＫ１と、ブロックＢＬＫ０またはブロックＢＬＫ１の第１メモリセルに、第１電圧ＶＳＳを印加した後に前記第１電圧より大きい第２電圧ＶＲＥＡＤを続けて印加し、前記第２電圧を印加した後に第３電圧ＶＣＧＲＶを印加するように構成される制御回路とを含み、前記制御回路は、前記第１メモリセルがブロックＢＬＫ０に含まれる場合、前記第１メモリセルがブロックＢＬＫ１に含まれる場合よりも、前記第２電圧を印加してからの時間が第１時間ΔＴ１１だけ早いタイミングで、前記第１メモリセルに前記第３電圧を印加するように構成される。【選択図】図１１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | SEMICONDUCTOR STORAGE DEVICE |
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