NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
To provide a nonvolatile memory device and a manufacturing method thereof capable of improving memory cell characteristics, ensuring uniformity, and increasing the degree of integration.SOLUTION: A manufacturing method of a nonvolatile memory device includes a step of forming a laminated structure S...
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| creator | KWON IL-YOUNG OH JIN-HO LEE SUHYOUNG GWON TAE-HONG BIN JIN-HO |
| description | To provide a nonvolatile memory device and a manufacturing method thereof capable of improving memory cell characteristics, ensuring uniformity, and increasing the degree of integration.SOLUTION: A manufacturing method of a nonvolatile memory device includes a step of forming a laminated structure SS" in which an interlayer insulating film 110 and a first material film are alternately laminated, a step of forming at least one channel hole 130 through the laminated structure, a step of forming a memory film pattern 140' along the channel hole, a step of trimming the surface of the memory film pattern, a step of oxidizing all of the trimmed memory film patterns to form at least a portion of the charge blocking film, and a step of forming a charge storage layer pattern 144' and a tunnel insulating layer pattern 146' on a charge blocking film pattern 142'''.SELECTED DRAWING: Figure 10A
【課題】メモリセル特性を改善し、均一性を確保でき、集積度増加が可能な不揮発性メモリ装置及びその製造方法を提供する。【解決手段】不揮発性メモリ装置の製造方法は、層間絶縁膜１１０及び第１の物質膜が交互に積層された積層構造物ＳＳ"を形成するステップと、積層構造物を貫通する少なくとも１つのチャネルホール１３０を形成するステップと、チャネルホールに沿ってメモリ膜パターン１４０'を形成するステップと、メモリ膜パターンの表面をトリミングするステップと、トリミングされたメモリ膜パターンの全部を酸化させて電荷遮断膜の少なくとも一部を形成するステップと、電荷遮断膜パターン１４２'''に電荷保存膜パターン１４４'及びトンネル絶縁膜パターン１４６'を形成するステップとを含む。【選択図】図１０Ａ |
| format | Patent |
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【課題】メモリセル特性を改善し、均一性を確保でき、集積度増加が可能な不揮発性メモリ装置及びその製造方法を提供する。【解決手段】不揮発性メモリ装置の製造方法は、層間絶縁膜１１０及び第１の物質膜が交互に積層された積層構造物ＳＳ"を形成するステップと、積層構造物を貫通する少なくとも１つのチャネルホール１３０を形成するステップと、チャネルホールに沿ってメモリ膜パターン１４０'を形成するステップと、メモリ膜パターンの表面をトリミングするステップと、トリミングされたメモリ膜パターンの全部を酸化させて電荷遮断膜の少なくとも一部を形成するステップと、電荷遮断膜パターン１４２'''に電荷保存膜パターン１４４'及びトンネル絶縁膜パターン１４６'を形成するステップとを含む。【選択図】図１０Ａ</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200806&DB=EPODOC&CC=JP&NR=2020120103A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200806&DB=EPODOC&CC=JP&NR=2020120103A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KWON IL-YOUNG</creatorcontrib><creatorcontrib>OH JIN-HO</creatorcontrib><creatorcontrib>LEE SUHYOUNG</creatorcontrib><creatorcontrib>GWON TAE-HONG</creatorcontrib><creatorcontrib>BIN JIN-HO</creatorcontrib><title>NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><description>To provide a nonvolatile memory device and a manufacturing method thereof capable of improving memory cell characteristics, ensuring uniformity, and increasing the degree of integration.SOLUTION: A manufacturing method of a nonvolatile memory device includes a step of forming a laminated structure SS" in which an interlayer insulating film 110 and a first material film are alternately laminated, a step of forming at least one channel hole 130 through the laminated structure, a step of forming a memory film pattern 140' along the channel hole, a step of trimming the surface of the memory film pattern, a step of oxidizing all of the trimmed memory film patterns to form at least a portion of the charge blocking film, and a step of forming a charge storage layer pattern 144' and a tunnel insulating layer pattern 146' on a charge blocking film pattern 142'''.SELECTED DRAWING: Figure 10A
【課題】メモリセル特性を改善し、均一性を確保でき、集積度増加が可能な不揮発性メモリ装置及びその製造方法を提供する。【解決手段】不揮発性メモリ装置の製造方法は、層間絶縁膜１１０及び第１の物質膜が交互に積層された積層構造物ＳＳ"を形成するステップと、積層構造物を貫通する少なくとも１つのチャネルホール１３０を形成するステップと、チャネルホールに沿ってメモリ膜パターン１４０'を形成するステップと、メモリ膜パターンの表面をトリミングするステップと、トリミングされたメモリ膜パターンの全部を酸化させて電荷遮断膜の少なくとも一部を形成するステップと、電荷遮断膜パターン１４２'''に電荷保存膜パターン１４４'及びトンネル絶縁膜パターン１４６'を形成するステップとを含む。【選択図】図１０Ａ</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDy8_cL8_dxDPH0cVXwdfX1D4pUcHEN83R2VXD0c1HwdfQLdXN0DgkN8vRzB8qHePi7KIR4uAa5-rvxMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAyMDQyAyMHY0JkoRABeaKXQ</recordid><startdate>20200806</startdate><enddate>20200806</enddate><creator>KWON IL-YOUNG</creator><creator>OH JIN-HO</creator><creator>LEE SUHYOUNG</creator><creator>GWON TAE-HONG</creator><creator>BIN JIN-HO</creator><scope>EVB</scope></search><sort><creationdate>20200806</creationdate><title>NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><author>KWON IL-YOUNG ; OH JIN-HO ; LEE SUHYOUNG ; GWON TAE-HONG ; BIN JIN-HO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2020120103A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KWON IL-YOUNG</creatorcontrib><creatorcontrib>OH JIN-HO</creatorcontrib><creatorcontrib>LEE SUHYOUNG</creatorcontrib><creatorcontrib>GWON TAE-HONG</creatorcontrib><creatorcontrib>BIN JIN-HO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KWON IL-YOUNG</au><au>OH JIN-HO</au><au>LEE SUHYOUNG</au><au>GWON TAE-HONG</au><au>BIN JIN-HO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><date>2020-08-06</date><risdate>2020</risdate><abstract>To provide a nonvolatile memory device and a manufacturing method thereof capable of improving memory cell characteristics, ensuring uniformity, and increasing the degree of integration.SOLUTION: A manufacturing method of a nonvolatile memory device includes a step of forming a laminated structure SS" in which an interlayer insulating film 110 and a first material film are alternately laminated, a step of forming at least one channel hole 130 through the laminated structure, a step of forming a memory film pattern 140' along the channel hole, a step of trimming the surface of the memory film pattern, a step of oxidizing all of the trimmed memory film patterns to form at least a portion of the charge blocking film, and a step of forming a charge storage layer pattern 144' and a tunnel insulating layer pattern 146' on a charge blocking film pattern 142'''.SELECTED DRAWING: Figure 10A
【課題】メモリセル特性を改善し、均一性を確保でき、集積度増加が可能な不揮発性メモリ装置及びその製造方法を提供する。【解決手段】不揮発性メモリ装置の製造方法は、層間絶縁膜１１０及び第１の物質膜が交互に積層された積層構造物ＳＳ"を形成するステップと、積層構造物を貫通する少なくとも１つのチャネルホール１３０を形成するステップと、チャネルホールに沿ってメモリ膜パターン１４０'を形成するステップと、メモリ膜パターンの表面をトリミングするステップと、トリミングされたメモリ膜パターンの全部を酸化させて電荷遮断膜の少なくとも一部を形成するステップと、電荷遮断膜パターン１４２'''に電荷保存膜パターン１４４'及びトンネル絶縁膜パターン１４６'を形成するステップとを含む。【選択図】図１０Ａ</abstract><oa>free_for_read</oa></addata></record> |
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| title | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF |
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