SEMICONDUCTOR INTEGRATED CIRCUIT
To reduce an effect of crosstalk noise by a method that does not affect miniaturization and improvement in integration.SOLUTION: The semiconductor integrated circuit includes: two or more sequential circuits; and a branch circuit for branching a signal from the sequential circuit into at least two o...
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creator | FUJIMORI KAZUYA |
description | To reduce an effect of crosstalk noise by a method that does not affect miniaturization and improvement in integration.SOLUTION: The semiconductor integrated circuit includes: two or more sequential circuits; and a branch circuit for branching a signal from the sequential circuit into at least two or more signals. The branch circuit is arranged near the sequential circuit. The branch circuit has at least one of outputs of the branch circuit connected to the ground potential when a selection signal is connected to the ground potential and a signal connected to the ground potential and the selection signal are arranged adjacent to both sides of a signal input to the sequential circuit.SELECTED DRAWING: Figure 1
【課題】 微細化、集積度向上に影響を与えない方法で、クロストークノイズの影響を削減する。【解決手段】 二つ以上の順序回路と、前記順序回路からの信号を少なくとも二つ以上の信号に分岐する分岐回路と、を備え、前記分岐回路は前記順序回路の近傍に配置され当該分岐回路は選択信号が接地電位に接続されるときに前記分岐回路の出力の少なくとも一つが接地電位に接続され接地電位に接続された信号と選択信号が順序回路に入力される信号の両側に隣接して配置されることを特徴とする半導体集積回路。【選択図】 図1 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2020043174A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2020043174A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2020043174A3</originalsourceid><addsrcrecordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRgYGJsaG5iaOxkQpAgBQrSKC</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>FUJIMORI KAZUYA</creator><creatorcontrib>FUJIMORI KAZUYA</creatorcontrib><description>To reduce an effect of crosstalk noise by a method that does not affect miniaturization and improvement in integration.SOLUTION: The semiconductor integrated circuit includes: two or more sequential circuits; and a branch circuit for branching a signal from the sequential circuit into at least two or more signals. The branch circuit is arranged near the sequential circuit. The branch circuit has at least one of outputs of the branch circuit connected to the ground potential when a selection signal is connected to the ground potential and a signal connected to the ground potential and the selection signal are arranged adjacent to both sides of a signal input to the sequential circuit.SELECTED DRAWING: Figure 1
【課題】 微細化、集積度向上に影響を与えない方法で、クロストークノイズの影響を削減する。【解決手段】 二つ以上の順序回路と、前記順序回路からの信号を少なくとも二つ以上の信号に分岐する分岐回路と、を備え、前記分岐回路は前記順序回路の近傍に配置され当該分岐回路は選択信号が接地電位に接続されるときに前記分岐回路の出力の少なくとも一つが接地電位に接続され接地電位に接続された信号と選択信号が順序回路に入力される信号の両側に隣接して配置されることを特徴とする半導体集積回路。【選択図】 図1</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200319&DB=EPODOC&CC=JP&NR=2020043174A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200319&DB=EPODOC&CC=JP&NR=2020043174A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FUJIMORI KAZUYA</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>To reduce an effect of crosstalk noise by a method that does not affect miniaturization and improvement in integration.SOLUTION: The semiconductor integrated circuit includes: two or more sequential circuits; and a branch circuit for branching a signal from the sequential circuit into at least two or more signals. The branch circuit is arranged near the sequential circuit. The branch circuit has at least one of outputs of the branch circuit connected to the ground potential when a selection signal is connected to the ground potential and a signal connected to the ground potential and the selection signal are arranged adjacent to both sides of a signal input to the sequential circuit.SELECTED DRAWING: Figure 1
【課題】 微細化、集積度向上に影響を与えない方法で、クロストークノイズの影響を削減する。【解決手段】 二つ以上の順序回路と、前記順序回路からの信号を少なくとも二つ以上の信号に分岐する分岐回路と、を備え、前記分岐回路は前記順序回路の近傍に配置され当該分岐回路は選択信号が接地電位に接続されるときに前記分岐回路の出力の少なくとも一つが接地電位に接続され接地電位に接続された信号と選択信号が順序回路に入力される信号の両側に隣接して配置されることを特徴とする半導体集積回路。【選択図】 図1</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRgYGJsaG5iaOxkQpAgBQrSKC</recordid><startdate>20200319</startdate><enddate>20200319</enddate><creator>FUJIMORI KAZUYA</creator><scope>EVB</scope></search><sort><creationdate>20200319</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>FUJIMORI KAZUYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2020043174A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FUJIMORI KAZUYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FUJIMORI KAZUYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2020-03-19</date><risdate>2020</risdate><abstract>To reduce an effect of crosstalk noise by a method that does not affect miniaturization and improvement in integration.SOLUTION: The semiconductor integrated circuit includes: two or more sequential circuits; and a branch circuit for branching a signal from the sequential circuit into at least two or more signals. The branch circuit is arranged near the sequential circuit. The branch circuit has at least one of outputs of the branch circuit connected to the ground potential when a selection signal is connected to the ground potential and a signal connected to the ground potential and the selection signal are arranged adjacent to both sides of a signal input to the sequential circuit.SELECTED DRAWING: Figure 1
【課題】 微細化、集積度向上に影響を与えない方法で、クロストークノイズの影響を削減する。【解決手段】 二つ以上の順序回路と、前記順序回路からの信号を少なくとも二つ以上の信号に分岐する分岐回路と、を備え、前記分岐回路は前記順序回路の近傍に配置され当該分岐回路は選択信号が接地電位に接続されるときに前記分岐回路の出力の少なくとも一つが接地電位に接続され接地電位に接続された信号と選択信号が順序回路に入力される信号の両側に隣接して配置されることを特徴とする半導体集積回路。【選択図】 図1</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT |
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