PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
To provide a package substrate having a structure suitable for realizing the mounting space (cavity) of a relatively deep chip, and to provide a manufacturing method thereof.SOLUTION: A package substrate comprises: a support member having first and second faces located oppositely, containing a cavit...
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| creator | KO YOUNG-KUK OH YOONG KIM SANG HUN KIM GYU MOOK |
| description | To provide a package substrate having a structure suitable for realizing the mounting space (cavity) of a relatively deep chip, and to provide a manufacturing method thereof.SOLUTION: A package substrate comprises: a support member having first and second faces located oppositely, containing a cavity coupling the first and second faces, and including a wiring structure having a portion projecting at least from the first face; a planarization layer placed on the first face of the support member, and having a coplanar face substantially flush with the projecting portion of the wiring structure; a conductive trace placed on the planarization layer and coupled with the wiring structure, and having a contact portion located in a region overlapping the cavity; and a coupling member placed on the first face of the support member so as to coat the conductive trace, and having a re-wiring layer coupled with the conductive trace.SELECTED DRAWING: Figure 1
【課題】相対的に深いチップの実装空間（キャビティ）を実現するのに適した構造を有するパッケージ基板及びその製造方法を提供する。【解決手段】本発明の一実施形態は、互いに反対に位置する第１及び第２面を有し、上記第１及び第２面を連結するキャビティを含み、少なくとも上記第１面から突出した部分を有する配線構造を備えた支持部材と、上記支持部材の第１面に配置され、上記配線構造の突出した部分と実質的に平坦な共面を有する平坦化層と、上記平坦化層上に配置されて上記配線構造と連結され、上記キャビティと重なった領域に位置するコンタクト部分を有する伝導性トレースと、上記伝導性トレースを覆うように上記支持部材の第１面に配置され、上記伝導性トレースと連結された再配線層を有する連結部材と、を含むパッケージ基板を提供する。【選択図】図１ |
| format | Patent |
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【課題】相対的に深いチップの実装空間（キャビティ）を実現するのに適した構造を有するパッケージ基板及びその製造方法を提供する。【解決手段】本発明の一実施形態は、互いに反対に位置する第１及び第２面を有し、上記第１及び第２面を連結するキャビティを含み、少なくとも上記第１面から突出した部分を有する配線構造を備えた支持部材と、上記支持部材の第１面に配置され、上記配線構造の突出した部分と実質的に平坦な共面を有する平坦化層と、上記平坦化層上に配置されて上記配線構造と連結され、上記キャビティと重なった領域に位置するコンタクト部分を有する伝導性トレースと、上記伝導性トレースを覆うように上記支持部材の第１面に配置され、上記伝導性トレースと連結された再配線層を有する連結部材と、を含むパッケージ基板を提供する。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191212&DB=EPODOC&CC=JP&NR=2019212881A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191212&DB=EPODOC&CC=JP&NR=2019212881A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KO YOUNG-KUK</creatorcontrib><creatorcontrib>OH YOONG</creatorcontrib><creatorcontrib>KIM SANG HUN</creatorcontrib><creatorcontrib>KIM GYU MOOK</creatorcontrib><title>PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF</title><description>To provide a package substrate having a structure suitable for realizing the mounting space (cavity) of a relatively deep chip, and to provide a manufacturing method thereof.SOLUTION: A package substrate comprises: a support member having first and second faces located oppositely, containing a cavity coupling the first and second faces, and including a wiring structure having a portion projecting at least from the first face; a planarization layer placed on the first face of the support member, and having a coplanar face substantially flush with the projecting portion of the wiring structure; a conductive trace placed on the planarization layer and coupled with the wiring structure, and having a contact portion located in a region overlapping the cavity; and a coupling member placed on the first face of the support member so as to coat the conductive trace, and having a re-wiring layer coupled with the conductive trace.SELECTED DRAWING: Figure 1
【課題】相対的に深いチップの実装空間（キャビティ）を実現するのに適した構造を有するパッケージ基板及びその製造方法を提供する。【解決手段】本発明の一実施形態は、互いに反対に位置する第１及び第２面を有し、上記第１及び第２面を連結するキャビティを含み、少なくとも上記第１面から突出した部分を有する配線構造を備えた支持部材と、上記支持部材の第１面に配置され、上記配線構造の突出した部分と実質的に平坦な共面を有する平坦化層と、上記平坦化層上に配置されて上記配線構造と連結され、上記キャビティと重なった領域に位置するコンタクト部分を有する伝導性トレースと、上記伝導性トレースを覆うように上記支持部材の第１面に配置され、上記伝導性トレースと連結された再配線層を有する連結部材と、を含むパッケージ基板を提供する。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKcHT2dnR3VQgOdQoOCXIMcVVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRCPFwDXL1d-NhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhpZGhkYWFoaOxkQpAgDHlSdP</recordid><startdate>20191212</startdate><enddate>20191212</enddate><creator>KO YOUNG-KUK</creator><creator>OH YOONG</creator><creator>KIM SANG HUN</creator><creator>KIM GYU MOOK</creator><scope>EVB</scope></search><sort><creationdate>20191212</creationdate><title>PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF</title><author>KO YOUNG-KUK ; OH YOONG ; KIM SANG HUN ; KIM GYU MOOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019212881A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KO YOUNG-KUK</creatorcontrib><creatorcontrib>OH YOONG</creatorcontrib><creatorcontrib>KIM SANG HUN</creatorcontrib><creatorcontrib>KIM GYU MOOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KO YOUNG-KUK</au><au>OH YOONG</au><au>KIM SANG HUN</au><au>KIM GYU MOOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF</title><date>2019-12-12</date><risdate>2019</risdate><abstract>To provide a package substrate having a structure suitable for realizing the mounting space (cavity) of a relatively deep chip, and to provide a manufacturing method thereof.SOLUTION: A package substrate comprises: a support member having first and second faces located oppositely, containing a cavity coupling the first and second faces, and including a wiring structure having a portion projecting at least from the first face; a planarization layer placed on the first face of the support member, and having a coplanar face substantially flush with the projecting portion of the wiring structure; a conductive trace placed on the planarization layer and coupled with the wiring structure, and having a contact portion located in a region overlapping the cavity; and a coupling member placed on the first face of the support member so as to coat the conductive trace, and having a re-wiring layer coupled with the conductive trace.SELECTED DRAWING: Figure 1
【課題】相対的に深いチップの実装空間（キャビティ）を実現するのに適した構造を有するパッケージ基板及びその製造方法を提供する。【解決手段】本発明の一実施形態は、互いに反対に位置する第１及び第２面を有し、上記第１及び第２面を連結するキャビティを含み、少なくとも上記第１面から突出した部分を有する配線構造を備えた支持部材と、上記支持部材の第１面に配置され、上記配線構造の突出した部分と実質的に平坦な共面を有する平坦化層と、上記平坦化層上に配置されて上記配線構造と連結され、上記キャビティと重なった領域に位置するコンタクト部分を有する伝導性トレースと、上記伝導性トレースを覆うように上記支持部材の第１面に配置され、上記伝導性トレースと連結された再配線層を有する連結部材と、を含むパッケージ基板を提供する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF |
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