MEMORY SYSTEM
To provide a memory system capable of improving processing capacity.SOLUTION: According to an embodiment, a memory system 1 includes a semiconductor storage device 100 having a memory cell array 18 including a memory cell MT, and a controller 200, which controls the semiconductor storage device 100,...
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| creator | OGASAWARA TAKASHI IWAI KATSUHIKO |
| description | To provide a memory system capable of improving processing capacity.SOLUTION: According to an embodiment, a memory system 1 includes a semiconductor storage device 100 having a memory cell array 18 including a memory cell MT, and a controller 200, which controls the semiconductor storage device 100, capable of creating second data on the basis of first data read from the memory cell MT. When a request for physical erase of the first data held in the memory cell MT is received from an external device 2, the controller 200 transmits one of the erase command and the write command for the second data to the semiconductor storage device 100.SELECTED DRAWING: Figure 14
【課題】処理能力を向上できるメモリシステムを提供する。【解決手段】実施形態によれば、メモリシステム１は、メモリセルＭＴを含むメモリセルアレイ１８を有する半導体記憶装置１００と、半導体記憶装置１００を制御し、メモリセルＭＴから読み出した第１データに基づいて第２データを作成可能なコントローラ２００とを含む。コントローラ２００は、外部機器２からメモリセルＭＴに保持された第１データの物理消去の要求を受信すると、半導体記憶装置１００に、消去命令及び第２データの書き込み命令の１つを送信する。【選択図】図１４ |
| format | Patent |
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【課題】処理能力を向上できるメモリシステムを提供する。【解決手段】実施形態によれば、メモリシステム１は、メモリセルＭＴを含むメモリセルアレイ１８を有する半導体記憶装置１００と、半導体記憶装置１００を制御し、メモリセルＭＴから読み出した第１データに基づいて第２データを作成可能なコントローラ２００とを含む。コントローラ２００は、外部機器２からメモリセルＭＴに保持された第１データの物理消去の要求を受信すると、半導体記憶装置１００に、消去命令及び第２データの書き込み命令の１つを送信する。【選択図】図１４</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190404&DB=EPODOC&CC=JP&NR=2019053805A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190404&DB=EPODOC&CC=JP&NR=2019053805A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OGASAWARA TAKASHI</creatorcontrib><creatorcontrib>IWAI KATSUHIKO</creatorcontrib><title>MEMORY SYSTEM</title><description>To provide a memory system capable of improving processing capacity.SOLUTION: According to an embodiment, a memory system 1 includes a semiconductor storage device 100 having a memory cell array 18 including a memory cell MT, and a controller 200, which controls the semiconductor storage device 100, capable of creating second data on the basis of first data read from the memory cell MT. When a request for physical erase of the first data held in the memory cell MT is received from an external device 2, the controller 200 transmits one of the erase command and the write command for the second data to the semiconductor storage device 100.SELECTED DRAWING: Figure 14
【課題】処理能力を向上できるメモリシステムを提供する。【解決手段】実施形態によれば、メモリシステム１は、メモリセルＭＴを含むメモリセルアレイ１８を有する半導体記憶装置１００と、半導体記憶装置１００を制御し、メモリセルＭＴから読み出した第１データに基づいて第２データを作成可能なコントローラ２００とを含む。コントローラ２００は、外部機器２からメモリセルＭＴに保持された第１データの物理消去の要求を受信すると、半導体記憶装置１００に、消去命令及び第２データの書き込み命令の１つを送信する。【選択図】図１４</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1dfX1D4pUCI4MDnH15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGlgamxhYGpo7GRCkCAPS-HUg</recordid><startdate>20190404</startdate><enddate>20190404</enddate><creator>OGASAWARA TAKASHI</creator><creator>IWAI KATSUHIKO</creator><scope>EVB</scope></search><sort><creationdate>20190404</creationdate><title>MEMORY SYSTEM</title><author>OGASAWARA TAKASHI ; IWAI KATSUHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019053805A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>OGASAWARA TAKASHI</creatorcontrib><creatorcontrib>IWAI KATSUHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OGASAWARA TAKASHI</au><au>IWAI KATSUHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY SYSTEM</title><date>2019-04-04</date><risdate>2019</risdate><abstract>To provide a memory system capable of improving processing capacity.SOLUTION: According to an embodiment, a memory system 1 includes a semiconductor storage device 100 having a memory cell array 18 including a memory cell MT, and a controller 200, which controls the semiconductor storage device 100, capable of creating second data on the basis of first data read from the memory cell MT. When a request for physical erase of the first data held in the memory cell MT is received from an external device 2, the controller 200 transmits one of the erase command and the write command for the second data to the semiconductor storage device 100.SELECTED DRAWING: Figure 14
【課題】処理能力を向上できるメモリシステムを提供する。【解決手段】実施形態によれば、メモリシステム１は、メモリセルＭＴを含むメモリセルアレイ１８を有する半導体記憶装置１００と、半導体記憶装置１００を制御し、メモリセルＭＴから読み出した第１データに基づいて第２データを作成可能なコントローラ２００とを含む。コントローラ２００は、外部機器２からメモリセルＭＴに保持された第１データの物理消去の要求を受信すると、半導体記憶装置１００に、消去命令及び第２データの書き込み命令の１つを送信する。【選択図】図１４</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; jpn |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
| title | MEMORY SYSTEM |
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