SEMICONDUCTOR APPARATUS, SECURITY PROCESSING EXECUTING APPARATUS, AND SECURITY PROCESSING EXECUTING METHOD
PROBLEM TO BE SOLVED: To prevent a central processing unit and a securing processing unit from simultaneously accessing to a non-volatile memory.SOLUTION: A data flash 13 has a secure region 31 and a user region 32. In the secure region 31, a plurality of security information for use in a security p...
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| creator | SHIODA SHIGEMASA ASARI SHINSUKE ITO KENICHI MORI YUKI |
| description | PROBLEM TO BE SOLVED: To prevent a central processing unit and a securing processing unit from simultaneously accessing to a non-volatile memory.SOLUTION: A data flash 13 has a secure region 31 and a user region 32. In the secure region 31, a plurality of security information for use in a security processing are stored. A security IP 12 reads out a part of the plurality of security information from the secure region 31 to store them in a secure RAM 22. When the security information for use in the security processing is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses them.SELECTED DRAWING: Figure 1
【課題】中央処理部とセキュリティ処理部とが不揮発性メモリに同時にアクセスすることを回避する。【解決手段】データフラッシュ１３は、セキュア領域３１とユーザ領域３２とを含む。セキュア領域３１には、セキュリティ処理で使用される複数のセキュリティ情報が記憶される。セキュリティＩＰ１２は、セキュア領域３１から複数のセキュリティ情報の一部を読み出してセキュアＲＡＭ２２に格納する。セキュアＩＰ１２は、セキュリティ処理で使用するセキュリティ情報がセキュアＲＡＭに記憶されている場合は、セキュアＲＡＭ２２からセキュリティ情報を読み出して使用する。【選択図】図１ |
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【課題】中央処理部とセキュリティ処理部とが不揮発性メモリに同時にアクセスすることを回避する。【解決手段】データフラッシュ１３は、セキュア領域３１とユーザ領域３２とを含む。セキュア領域３１には、セキュリティ処理で使用される複数のセキュリティ情報が記憶される。セキュリティＩＰ１２は、セキュア領域３１から複数のセキュリティ情報の一部を読み出してセキュアＲＡＭ２２に格納する。セキュアＩＰ１２は、セキュリティ処理で使用するセキュリティ情報がセキュアＲＡＭに記憶されている場合は、セキュアＲＡＭ２２からセキュリティ情報を読み出して使用する。【選択図】図１</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180705&DB=EPODOC&CC=JP&NR=2018106628A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180705&DB=EPODOC&CC=JP&NR=2018106628A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIODA SHIGEMASA</creatorcontrib><creatorcontrib>ASARI SHINSUKE</creatorcontrib><creatorcontrib>ITO KENICHI</creatorcontrib><creatorcontrib>MORI YUKI</creatorcontrib><title>SEMICONDUCTOR APPARATUS, SECURITY PROCESSING EXECUTING APPARATUS, AND SECURITY PROCESSING EXECUTING METHOD</title><description>PROBLEM TO BE SOLVED: To prevent a central processing unit and a securing processing unit from simultaneously accessing to a non-volatile memory.SOLUTION: A data flash 13 has a secure region 31 and a user region 32. In the secure region 31, a plurality of security information for use in a security processing are stored. A security IP 12 reads out a part of the plurality of security information from the secure region 31 to store them in a secure RAM 22. When the security information for use in the security processing is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses them.SELECTED DRAWING: Figure 1
【課題】中央処理部とセキュリティ処理部とが不揮発性メモリに同時にアクセスすることを回避する。【解決手段】データフラッシュ１３は、セキュア領域３１とユーザ領域３２とを含む。セキュア領域３１には、セキュリティ処理で使用される複数のセキュリティ情報が記憶される。セキュリティＩＰ１２は、セキュア領域３１から複数のセキュリティ情報の一部を読み出してセキュアＲＡＭ２２に格納する。セキュアＩＰ１２は、セキュリティ処理で使用するセキュリティ情報がセキュアＲＡＭに記憶されている場合は、セキュアＲＡＭ２２からセキュリティ情報を読み出して使用する。【選択図】図１</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZMgKdvX1dPb3cwl1DvEPUnAMCHAMcgwJDdZRCHZ1Dg3yDIlUCAjyd3YNDvb0c1dwjQAKhoBYSAod_VwIKPZ1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhhaGBmZmRhaOxkQpAgB5lzd4</recordid><startdate>20180705</startdate><enddate>20180705</enddate><creator>SHIODA SHIGEMASA</creator><creator>ASARI SHINSUKE</creator><creator>ITO KENICHI</creator><creator>MORI YUKI</creator><scope>EVB</scope></search><sort><creationdate>20180705</creationdate><title>SEMICONDUCTOR APPARATUS, SECURITY PROCESSING EXECUTING APPARATUS, AND SECURITY PROCESSING EXECUTING METHOD</title><author>SHIODA SHIGEMASA ; ASARI SHINSUKE ; ITO KENICHI ; MORI YUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2018106628A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIODA SHIGEMASA</creatorcontrib><creatorcontrib>ASARI SHINSUKE</creatorcontrib><creatorcontrib>ITO KENICHI</creatorcontrib><creatorcontrib>MORI YUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIODA SHIGEMASA</au><au>ASARI SHINSUKE</au><au>ITO KENICHI</au><au>MORI YUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR APPARATUS, SECURITY PROCESSING EXECUTING APPARATUS, AND SECURITY PROCESSING EXECUTING METHOD</title><date>2018-07-05</date><risdate>2018</risdate><abstract>PROBLEM TO BE SOLVED: To prevent a central processing unit and a securing processing unit from simultaneously accessing to a non-volatile memory.SOLUTION: A data flash 13 has a secure region 31 and a user region 32. In the secure region 31, a plurality of security information for use in a security processing are stored. A security IP 12 reads out a part of the plurality of security information from the secure region 31 to store them in a secure RAM 22. When the security information for use in the security processing is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses them.SELECTED DRAWING: Figure 1
【課題】中央処理部とセキュリティ処理部とが不揮発性メモリに同時にアクセスすることを回避する。【解決手段】データフラッシュ１３は、セキュア領域３１とユーザ領域３２とを含む。セキュア領域３１には、セキュリティ処理で使用される複数のセキュリティ情報が記憶される。セキュリティＩＰ１２は、セキュア領域３１から複数のセキュリティ情報の一部を読み出してセキュアＲＡＭ２２に格納する。セキュアＩＰ１２は、セキュリティ処理で使用するセキュリティ情報がセキュアＲＡＭに記憶されている場合は、セキュアＲＡＭ２２からセキュリティ情報を読み出して使用する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | SEMICONDUCTOR APPARATUS, SECURITY PROCESSING EXECUTING APPARATUS, AND SECURITY PROCESSING EXECUTING METHOD |
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