SEMICONDUCTOR DEVICE MANUFACTURING METHOD
PROBLEM TO BE SOLVED: To prevent generation of a crack in a layer which covers a semiconductor layer when performing heat treatment on the semiconductor layer.SOLUTION: A manufacturing method of a semiconductor device 100 comprises: a step (P101) of forming on a semiconductor layer 111 consisting ma...
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creator | NIWA SHIGEKI FUJII TAKAHIRO OZAKI MASAYOSHI |
description | PROBLEM TO BE SOLVED: To prevent generation of a crack in a layer which covers a semiconductor layer when performing heat treatment on the semiconductor layer.SOLUTION: A manufacturing method of a semiconductor device 100 comprises: a step (P101) of forming on a semiconductor layer 111 consisting mainly of a group III nitride semiconductor, at least part Mt11 of a cap layer Mc1 consisting mainly of a nitride; a step (P103) of ion implanting a p-type impurity into the semiconductor layer 111 where at least the part Mt11 of the cap layer Mc1 is formed; a step (P106) of forming as a surface layer, a block layer Mb1 having a thermal expansion coefficient larger than that of the cap layer Mc1 on the cap layer Mc1; and a step (P107) of heating the semiconductor layer 111 where the block layer Mb1 as the surface layer is formed to activate the p-type impurity.SELECTED DRAWING: Figure 2
【課題】半導体層を熱処理する際に、半導体層を覆う層にクラックが入らないようにする。【解決手段】半導体装置100の製造方法であって、主としてIII族窒化物半導体からなる半導体層111の上に、主として窒化物で構成されるキャップ層Mc1の少なくとも一部Mt11を形成する工程(P101)と、前記キャップ層Mc1の少なくとも一部Mt11が形成された半導体層111にp型不純物をイオン注入する工程(P103)と、表層として、前記キャップ層Mc1よりも熱膨張係数が大きいブロック層Mb1を、前記キャップ層Mc1の上に形成する工程P106と、前記表層としての前記ブロック層Mb1が形成された半導体層111を加熱してp型不純物を活性化させる工程(P107)と、を備える。【選択図】図2 |
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【課題】半導体層を熱処理する際に、半導体層を覆う層にクラックが入らないようにする。【解決手段】半導体装置100の製造方法であって、主としてIII族窒化物半導体からなる半導体層111の上に、主として窒化物で構成されるキャップ層Mc1の少なくとも一部Mt11を形成する工程(P101)と、前記キャップ層Mc1の少なくとも一部Mt11が形成された半導体層111にp型不純物をイオン注入する工程(P103)と、表層として、前記キャップ層Mc1よりも熱膨張係数が大きいブロック層Mb1を、前記キャップ層Mc1の上に形成する工程P106と、前記表層としての前記ブロック層Mb1が形成された半導体層111を加熱してp型不純物を活性化させる工程(P107)と、を備える。【選択図】図2</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180405&DB=EPODOC&CC=JP&NR=2018056257A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180405&DB=EPODOC&CC=JP&NR=2018056257A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NIWA SHIGEKI</creatorcontrib><creatorcontrib>FUJII TAKAHIRO</creatorcontrib><creatorcontrib>OZAKI MASAYOSHI</creatorcontrib><title>SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To prevent generation of a crack in a layer which covers a semiconductor layer when performing heat treatment on the semiconductor layer.SOLUTION: A manufacturing method of a semiconductor device 100 comprises: a step (P101) of forming on a semiconductor layer 111 consisting mainly of a group III nitride semiconductor, at least part Mt11 of a cap layer Mc1 consisting mainly of a nitride; a step (P103) of ion implanting a p-type impurity into the semiconductor layer 111 where at least the part Mt11 of the cap layer Mc1 is formed; a step (P106) of forming as a surface layer, a block layer Mb1 having a thermal expansion coefficient larger than that of the cap layer Mc1 on the cap layer Mc1; and a step (P107) of heating the semiconductor layer 111 where the block layer Mb1 as the surface layer is formed to activate the p-type impurity.SELECTED DRAWING: Figure 2
【課題】半導体層を熱処理する際に、半導体層を覆う層にクラックが入らないようにする。【解決手段】半導体装置100の製造方法であって、主としてIII族窒化物半導体からなる半導体層111の上に、主として窒化物で構成されるキャップ層Mc1の少なくとも一部Mt11を形成する工程(P101)と、前記キャップ層Mc1の少なくとも一部Mt11が形成された半導体層111にp型不純物をイオン注入する工程(P103)と、表層として、前記キャップ層Mc1よりも熱膨張係数が大きいブロック層Mb1を、前記キャップ層Mc1の上に形成する工程P106と、前記表層としての前記ブロック層Mb1が形成された半導体層111を加熱してp型不純物を活性化させる工程(P107)と、を備える。【選択図】図2</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAMdvX1dPb3cwl1DvEPUnBxDfN0dlXwdfQLdXN0DgkN8vRzV_B1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhhYGpmZGpuaOxkQpAgCPBiUQ</recordid><startdate>20180405</startdate><enddate>20180405</enddate><creator>NIWA SHIGEKI</creator><creator>FUJII TAKAHIRO</creator><creator>OZAKI MASAYOSHI</creator><scope>EVB</scope></search><sort><creationdate>20180405</creationdate><title>SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><author>NIWA SHIGEKI ; FUJII TAKAHIRO ; OZAKI MASAYOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2018056257A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NIWA SHIGEKI</creatorcontrib><creatorcontrib>FUJII TAKAHIRO</creatorcontrib><creatorcontrib>OZAKI MASAYOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NIWA SHIGEKI</au><au>FUJII TAKAHIRO</au><au>OZAKI MASAYOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><date>2018-04-05</date><risdate>2018</risdate><abstract>PROBLEM TO BE SOLVED: To prevent generation of a crack in a layer which covers a semiconductor layer when performing heat treatment on the semiconductor layer.SOLUTION: A manufacturing method of a semiconductor device 100 comprises: a step (P101) of forming on a semiconductor layer 111 consisting mainly of a group III nitride semiconductor, at least part Mt11 of a cap layer Mc1 consisting mainly of a nitride; a step (P103) of ion implanting a p-type impurity into the semiconductor layer 111 where at least the part Mt11 of the cap layer Mc1 is formed; a step (P106) of forming as a surface layer, a block layer Mb1 having a thermal expansion coefficient larger than that of the cap layer Mc1 on the cap layer Mc1; and a step (P107) of heating the semiconductor layer 111 where the block layer Mb1 as the surface layer is formed to activate the p-type impurity.SELECTED DRAWING: Figure 2
【課題】半導体層を熱処理する際に、半導体層を覆う層にクラックが入らないようにする。【解決手段】半導体装置100の製造方法であって、主としてIII族窒化物半導体からなる半導体層111の上に、主として窒化物で構成されるキャップ層Mc1の少なくとも一部Mt11を形成する工程(P101)と、前記キャップ層Mc1の少なくとも一部Mt11が形成された半導体層111にp型不純物をイオン注入する工程(P103)と、表層として、前記キャップ層Mc1よりも熱膨張係数が大きいブロック層Mb1を、前記キャップ層Mc1の上に形成する工程P106と、前記表層としての前記ブロック層Mb1が形成された半導体層111を加熱してp型不純物を活性化させる工程(P107)と、を備える。【選択図】図2</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE MANUFACTURING METHOD |
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