MANUFACTURING METHOD FOR SEMICONDUCTOR
PROBLEM TO BE SOLVED: To provide a technique that makes it possible to suppress the diffusion of solder into a semiconductor device without increasing the size of the semiconductor.SOLUTION: An electrode layer formed on a semiconductor element comprises: a first barrier layer containing Ni: an inter...
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| creator | MUKAI FUMIYA |
| description | PROBLEM TO BE SOLVED: To provide a technique that makes it possible to suppress the diffusion of solder into a semiconductor device without increasing the size of the semiconductor.SOLUTION: An electrode layer formed on a semiconductor element comprises: a first barrier layer containing Ni: an intermediate layer layered on the first barrier layer and containing Sn; and a second barrier layer layered on the intermediate layer and containing Ni. The semiconductor element, in which the first barrier layer, intermediate layer, and second barrier layer are arranged in order away from a semiconductor substrate 2, is annealed to form an alloy of Ni and Sn around the surface of the intermediate layer. The second barrier layer of the annealed semiconductor element is soldered on the mounting substrate by reflowing.SELECTED DRAWING: Figure 3
【課題】半導体装置を大型化しなくても、半導体装置内へのはんだの拡散を抑制可能な技術を提供する。【解決手段】半導体素子に形成した電極層は、Ｎｉを含む第１バリア層と、第１バリア層上に積層されているとともにＳｎを含む中間層と、中間層上に積層されているとともにＮｉを含む第２バリア層を備えている。半導体基板２から離れる方向に向かって、第１バリア層、中間層、第２バリア層が順に並んでいる、その半導体素子をアニール処理し、中間層上を中心にしてＮｉとＳｎの合金を形成する。アニール処理した後の半導体素子の第２バリア層をリフローにより実装基板にはんだ付けする。【選択図】図３ |
| format | Patent |
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【課題】半導体装置を大型化しなくても、半導体装置内へのはんだの拡散を抑制可能な技術を提供する。【解決手段】半導体素子に形成した電極層は、Ｎｉを含む第１バリア層と、第１バリア層上に積層されているとともにＳｎを含む中間層と、中間層上に積層されているとともにＮｉを含む第２バリア層を備えている。半導体基板２から離れる方向に向かって、第１バリア層、中間層、第２バリア層が順に並んでいる、その半導体素子をアニール処理し、中間層上を中心にしてＮｉとＳｎの合金を形成する。アニール処理した後の半導体素子の第２バリア層をリフローにより実装基板にはんだ付けする。【選択図】図３</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180322&DB=EPODOC&CC=JP&NR=2018046252A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180322&DB=EPODOC&CC=JP&NR=2018046252A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MUKAI FUMIYA</creatorcontrib><title>MANUFACTURING METHOD FOR SEMICONDUCTOR</title><description>PROBLEM TO BE SOLVED: To provide a technique that makes it possible to suppress the diffusion of solder into a semiconductor device without increasing the size of the semiconductor.SOLUTION: An electrode layer formed on a semiconductor element comprises: a first barrier layer containing Ni: an intermediate layer layered on the first barrier layer and containing Sn; and a second barrier layer layered on the intermediate layer and containing Ni. The semiconductor element, in which the first barrier layer, intermediate layer, and second barrier layer are arranged in order away from a semiconductor substrate 2, is annealed to form an alloy of Ni and Sn around the surface of the intermediate layer. The second barrier layer of the annealed semiconductor element is soldered on the mounting substrate by reflowing.SELECTED DRAWING: Figure 3
【課題】半導体装置を大型化しなくても、半導体装置内へのはんだの拡散を抑制可能な技術を提供する。【解決手段】半導体素子に形成した電極層は、Ｎｉを含む第１バリア層と、第１バリア層上に積層されているとともにＳｎを含む中間層と、中間層上に積層されているとともにＮｉを含む第２バリア層を備えている。半導体基板２から離れる方向に向かって、第１バリア層、中間層、第２バリア層が順に並んでいる、その半導体素子をアニール処理し、中間層上を中心にしてＮｉとＳｎの合金を形成する。アニール処理した後の半導体素子の第２バリア層をリフローにより実装基板にはんだ付けする。【選択図】図３</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDzdfQLdXN0DgkN8vRzV_B1DfHwd1Fw8w9SCHb19XT293MJdQ7xD-JhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhhYGJmZGpkaOxkQpAgAicSQ4</recordid><startdate>20180322</startdate><enddate>20180322</enddate><creator>MUKAI FUMIYA</creator><scope>EVB</scope></search><sort><creationdate>20180322</creationdate><title>MANUFACTURING METHOD FOR SEMICONDUCTOR</title><author>MUKAI FUMIYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2018046252A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MUKAI FUMIYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MUKAI FUMIYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURING METHOD FOR SEMICONDUCTOR</title><date>2018-03-22</date><risdate>2018</risdate><abstract>PROBLEM TO BE SOLVED: To provide a technique that makes it possible to suppress the diffusion of solder into a semiconductor device without increasing the size of the semiconductor.SOLUTION: An electrode layer formed on a semiconductor element comprises: a first barrier layer containing Ni: an intermediate layer layered on the first barrier layer and containing Sn; and a second barrier layer layered on the intermediate layer and containing Ni. The semiconductor element, in which the first barrier layer, intermediate layer, and second barrier layer are arranged in order away from a semiconductor substrate 2, is annealed to form an alloy of Ni and Sn around the surface of the intermediate layer. The second barrier layer of the annealed semiconductor element is soldered on the mounting substrate by reflowing.SELECTED DRAWING: Figure 3
【課題】半導体装置を大型化しなくても、半導体装置内へのはんだの拡散を抑制可能な技術を提供する。【解決手段】半導体素子に形成した電極層は、Ｎｉを含む第１バリア層と、第１バリア層上に積層されているとともにＳｎを含む中間層と、中間層上に積層されているとともにＮｉを含む第２バリア層を備えている。半導体基板２から離れる方向に向かって、第１バリア層、中間層、第２バリア層が順に並んでいる、その半導体素子をアニール処理し、中間層上を中心にしてＮｉとＳｎの合金を形成する。アニール処理した後の半導体素子の第２バリア層をリフローにより実装基板にはんだ付けする。【選択図】図３</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | MANUFACTURING METHOD FOR SEMICONDUCTOR |
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