ABNORMALITY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS
PROBLEM TO BE SOLVED: To accurately detect abnormality in substrate processing.SOLUTION: An abnormality detection method includes the steps of: calculating three standard deviation values concerning process conditions collected at predetermined intervals on the basis of log information obtained when...
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| creator | MOCHIZUKI HIROO OKI TATSUYA |
| description | PROBLEM TO BE SOLVED: To accurately detect abnormality in substrate processing.SOLUTION: An abnormality detection method includes the steps of: calculating three standard deviation values concerning process conditions collected at predetermined intervals on the basis of log information obtained when a plurality of normally-processed substrates are processed and calculating at least one of an upper limit and a lower limit of abnormality detection on the basis of the calculated three standard deviation values; and detecting abnormality in substrate processing on the basis of at least one of the upper limit and the lower limit of abnormality detection calculated.SELECTED DRAWING: Figure 5
【課題】基板の処理における異常を精度良く検知することを目的とする。【解決手段】正常に処理された複数枚の基板を処理したときのログ情報に基づき所定の間隔で収集したプロセス条件についての３標準偏差値を算出し、算出した前記３標準偏差値に基づき異常検知の上限値及び下限値の少なくともいずれかを算出する工程と、算出した前記異常検知の上限値及び下限値の少なくともいずれかに基づき基板の処理の異常を検出する工程と、を有する異常検知方法が提供される。【選択図】図５ |
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【課題】基板の処理における異常を精度良く検知することを目的とする。【解決手段】正常に処理された複数枚の基板を処理したときのログ情報に基づき所定の間隔で収集したプロセス条件についての３標準偏差値を算出し、算出した前記３標準偏差値に基づき異常検知の上限値及び下限値の少なくともいずれかを算出する工程と、算出した前記異常検知の上限値及び下限値の少なくともいずれかに基づき基板の処理の異常を検出する工程と、を有する異常検知方法が提供される。【選択図】図５</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; REGULATING ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180315&DB=EPODOC&CC=JP&NR=2018041217A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180315&DB=EPODOC&CC=JP&NR=2018041217A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MOCHIZUKI HIROO</creatorcontrib><creatorcontrib>OKI TATSUYA</creatorcontrib><title>ABNORMALITY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS</title><description>PROBLEM TO BE SOLVED: To accurately detect abnormality in substrate processing.SOLUTION: An abnormality detection method includes the steps of: calculating three standard deviation values concerning process conditions collected at predetermined intervals on the basis of log information obtained when a plurality of normally-processed substrates are processed and calculating at least one of an upper limit and a lower limit of abnormality detection on the basis of the calculated three standard deviation values; and detecting abnormality in substrate processing on the basis of at least one of the upper limit and the lower limit of abnormality detection calculated.SELECTED DRAWING: Figure 5
【課題】基板の処理における異常を精度良く検知することを目的とする。【解決手段】正常に処理された複数枚の基板を処理したときのログ情報に基づき所定の間隔で収集したプロセス条件についての３標準偏差値を算出し、算出した前記３標準偏差値に基づき異常検知の上限値及び下限値の少なくともいずれかを算出する工程と、算出した前記異常検知の上限値及び下限値の少なくともいずれかに基づき基板の処理の異常を検出する工程と、を有する異常検知方法が提供される。【選択図】図５</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBzdPLzD_J19PEMiVRwcQ1xdQ7x9PdT8HUN8fB3UXD0c1EIdvX1dPb3cwl1DvEPUvB19At1c3QOCQ3y9HNXcAwIcAxyDAkN5mFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGFgYmhkaG5o7GRCkCADxkLS4</recordid><startdate>20180315</startdate><enddate>20180315</enddate><creator>MOCHIZUKI HIROO</creator><creator>OKI TATSUYA</creator><scope>EVB</scope></search><sort><creationdate>20180315</creationdate><title>ABNORMALITY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS</title><author>MOCHIZUKI HIROO ; OKI TATSUYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2018041217A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MOCHIZUKI HIROO</creatorcontrib><creatorcontrib>OKI TATSUYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MOCHIZUKI HIROO</au><au>OKI TATSUYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ABNORMALITY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS</title><date>2018-03-15</date><risdate>2018</risdate><abstract>PROBLEM TO BE SOLVED: To accurately detect abnormality in substrate processing.SOLUTION: An abnormality detection method includes the steps of: calculating three standard deviation values concerning process conditions collected at predetermined intervals on the basis of log information obtained when a plurality of normally-processed substrates are processed and calculating at least one of an upper limit and a lower limit of abnormality detection on the basis of the calculated three standard deviation values; and detecting abnormality in substrate processing on the basis of at least one of the upper limit and the lower limit of abnormality detection calculated.SELECTED DRAWING: Figure 5
【課題】基板の処理における異常を精度良く検知することを目的とする。【解決手段】正常に処理された複数枚の基板を処理したときのログ情報に基づき所定の間隔で収集したプロセス条件についての３標準偏差値を算出し、算出した前記３標準偏差値に基づき異常検知の上限値及び下限値の少なくともいずれかを算出する工程と、算出した前記異常検知の上限値及び下限値の少なくともいずれかに基づき基板の処理の異常を検出する工程と、を有する異常検知方法が提供される。【選択図】図５</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING SEMICONDUCTOR DEVICES |
| title | ABNORMALITY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS |
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