METHOD FOR FACILITATING CUSTOM LAYOUT OF IC DESIGN, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND METHOD FOR FACILITATING CUSTOM LAYOUT OF MULTIGATE DEVICES
PROBLEM TO BE SOLVED: To provide systems and techniques for facilitating a layout of an integrated circuit (IC) design drawing.SOLUTION: A distinct color pattern can be assigned to a set of shapes in a layout of an IC design drawing that correspond to a net. Next, the layout of the IC design drawing...
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creator | ROBERT B LEFFERTS |
description | PROBLEM TO BE SOLVED: To provide systems and techniques for facilitating a layout of an integrated circuit (IC) design drawing.SOLUTION: A distinct color pattern can be assigned to a set of shapes in a layout of an IC design drawing that correspond to a net. Next, the layout of the IC design drawing can be displayed in a graphical user interface (GUI) of an IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of device contacts so that the diffusion region is aligned with respect to a set of fin tracks, where each fin of each multigate device is located on a fin track.SELECTED DRAWING: Figure 5B
【課題】集積回路(IC)設計図のレイアウトを容易にするためのシステムおよび技術を提供する。【解決手段】特異な色パターンを、ネットに対応する、IC設計図のレイアウト内の一組の形状に割当てることができる。次に、IC設計図のレイアウトを、IC設計ツールのグラフィカルユーザインターフェイス(GUI)に表示することができる。いくつかの実施形態は、マルチゲート素子の拡散領域を、この拡散領域が一組のフィントラックに対して位置合わせされるように、素子コンタクトの場所に対して移動させることができ、各マルチゲート素子の各フィンはフィントラック上に位置する。【選択図】図5B |
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【課題】集積回路(IC)設計図のレイアウトを容易にするためのシステムおよび技術を提供する。【解決手段】特異な色パターンを、ネットに対応する、IC設計図のレイアウト内の一組の形状に割当てることができる。次に、IC設計図のレイアウトを、IC設計ツールのグラフィカルユーザインターフェイス(GUI)に表示することができる。いくつかの実施形態は、マルチゲート素子の拡散領域を、この拡散領域が一組のフィントラックに対して位置合わせされるように、素子コンタクトの場所に対して移動させることができ、各マルチゲート素子の各フィンはフィントラック上に位置する。【選択図】図5B</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171019&DB=EPODOC&CC=JP&NR=2017191598A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171019&DB=EPODOC&CC=JP&NR=2017191598A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROBERT B LEFFERTS</creatorcontrib><title>METHOD FOR FACILITATING CUSTOM LAYOUT OF IC DESIGN, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND METHOD FOR FACILITATING CUSTOM LAYOUT OF MULTIGATE DEVICES</title><description>PROBLEM TO BE SOLVED: To provide systems and techniques for facilitating a layout of an integrated circuit (IC) design drawing.SOLUTION: A distinct color pattern can be assigned to a set of shapes in a layout of an IC design drawing that correspond to a net. Next, the layout of the IC design drawing can be displayed in a graphical user interface (GUI) of an IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of device contacts so that the diffusion region is aligned with respect to a set of fin tracks, where each fin of each multigate device is located on a fin track.SELECTED DRAWING: Figure 5B
【課題】集積回路(IC)設計図のレイアウトを容易にするためのシステムおよび技術を提供する。【解決手段】特異な色パターンを、ネットに対応する、IC設計図のレイアウト内の一組の形状に割当てることができる。次に、IC設計図のレイアウトを、IC設計ツールのグラフィカルユーザインターフェイス(GUI)に表示することができる。いくつかの実施形態は、マルチゲート素子の拡散領域を、この拡散領域が一組のフィントラックに対して位置合わせされるように、素子コンタクトの場所に対して移動させることができ、各マルチゲート素子の各フィンはフィントラック上に位置する。【選択図】図5B</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjTEKwkAQANNYiPqHxToBo4harnebZCV3Fy57glUQOStRIf7Ij5rCB6SaZoaZJl9DUjkNhfNQoOKaBYVtCSq04gzUeHFBwBXACjS1XNoUrLOZeLQti_MXUM40QchnnlDjsSYYUo8lgSHNwaSAVsPokQm1cIlCw-_Mitp5MrlfH31c_DlLlgWJqrL4fnWxf19v8Rk_3alZr_Jdfsi3hz1uRkk_3GRGVw</recordid><startdate>20171019</startdate><enddate>20171019</enddate><creator>ROBERT B LEFFERTS</creator><scope>EVB</scope></search><sort><creationdate>20171019</creationdate><title>METHOD FOR FACILITATING CUSTOM LAYOUT OF IC DESIGN, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND METHOD FOR FACILITATING CUSTOM LAYOUT OF MULTIGATE DEVICES</title><author>ROBERT B LEFFERTS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2017191598A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ROBERT B LEFFERTS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROBERT B LEFFERTS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR FACILITATING CUSTOM LAYOUT OF IC DESIGN, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND METHOD FOR FACILITATING CUSTOM LAYOUT OF MULTIGATE DEVICES</title><date>2017-10-19</date><risdate>2017</risdate><abstract>PROBLEM TO BE SOLVED: To provide systems and techniques for facilitating a layout of an integrated circuit (IC) design drawing.SOLUTION: A distinct color pattern can be assigned to a set of shapes in a layout of an IC design drawing that correspond to a net. Next, the layout of the IC design drawing can be displayed in a graphical user interface (GUI) of an IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of device contacts so that the diffusion region is aligned with respect to a set of fin tracks, where each fin of each multigate device is located on a fin track.SELECTED DRAWING: Figure 5B
【課題】集積回路(IC)設計図のレイアウトを容易にするためのシステムおよび技術を提供する。【解決手段】特異な色パターンを、ネットに対応する、IC設計図のレイアウト内の一組の形状に割当てることができる。次に、IC設計図のレイアウトを、IC設計ツールのグラフィカルユーザインターフェイス(GUI)に表示することができる。いくつかの実施形態は、マルチゲート素子の拡散領域を、この拡散領域が一組のフィントラックに対して位置合わせされるように、素子コンタクトの場所に対して移動させることができ、各マルチゲート素子の各フィンはフィントラック上に位置する。【選択図】図5B</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
title | METHOD FOR FACILITATING CUSTOM LAYOUT OF IC DESIGN, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND METHOD FOR FACILITATING CUSTOM LAYOUT OF MULTIGATE DEVICES |
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