WAFER PROCESSING METHOD
PROBLEM TO BE SOLVED: To provide a wafer processing method which can generate a high quality device chip from a WL-CSP wafer.SOLUTION: A wafer processing method that divides a wafer 11, on which devices are formed on each region on the surface partitioned by a plurality of division schedule lines fo...
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| creator | SUGITANI TETSUKAZU RIKU KIN AIDA KANA |
| description | PROBLEM TO BE SOLVED: To provide a wafer processing method which can generate a high quality device chip from a WL-CSP wafer.SOLUTION: A wafer processing method that divides a wafer 11, on which devices are formed on each region on the surface partitioned by a plurality of division schedule lines formed in a lattice shape, into chips includes: forming a groove 19 having a depth equivalent to a finishing thickness of a chip along a division schedule line; covering a surface of a wafer with a mold resin 21 and embedding the mold resin in the groove; arranging a protective member 23 on the surface of the wafer; sucking and holding the wafer with a chuck table through the protective member, grinding a rear face of the wafer, and exposing the mold resin embedded in the groove; forming a division starting point 25 along the division schedule line in the center of the resin exposed to the rear face; and mounting the wafer on a base 40 having flexibility, imparting an external force from the surface side, and dividing the wafer into individual device chips having the outer periphery surrounded by the resin.SELECTED DRAWING: Figure 9
【課題】ＷＬ−ＣＳＰウエーハから品質の良いデバイスチップを生成することのできるウエーハの加工方法の提供。【解決手段】格子状に形成された複数の分割予定ラインによって区画された表面の各領域にデバイスが形成されたウエーハ１１を個々のチップに分割する加工方法であって、チップの仕上がり厚さに相当する深さを有する溝１９を分割予定ラインに沿って形成する工程と、ウエーハの表面をモールド樹脂２１で被覆して溝に樹脂を埋設する工程と、ウエーハの表面に保護部材２３を配設する工程と、保護部材を介してウエーハをチャックテーブルで吸引保持し、裏面を研削して溝中に埋設された樹脂を露出させる工程と、裏面に露出した樹脂の中央に分割予定ラインに沿って分割起点２５を形成する工程と、可撓性を有する基台４０上にウエーハを載置し、表面側から外力を付与してウエーハを樹脂によって囲繞された外周を有する個々のチップに分割する工程を含む。【選択図】図９ |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2017107986A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2017107986A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2017107986A3</originalsourceid><addsrcrecordid>eNrjZBAPd3RzDVIICPJ3dg0O9vRzV_B1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhuaGBuaWFmaOxkQpAgAWdR_3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WAFER PROCESSING METHOD</title><source>esp@cenet</source><creator>SUGITANI TETSUKAZU ; RIKU KIN ; AIDA KANA</creator><creatorcontrib>SUGITANI TETSUKAZU ; RIKU KIN ; AIDA KANA</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wafer processing method which can generate a high quality device chip from a WL-CSP wafer.SOLUTION: A wafer processing method that divides a wafer 11, on which devices are formed on each region on the surface partitioned by a plurality of division schedule lines formed in a lattice shape, into chips includes: forming a groove 19 having a depth equivalent to a finishing thickness of a chip along a division schedule line; covering a surface of a wafer with a mold resin 21 and embedding the mold resin in the groove; arranging a protective member 23 on the surface of the wafer; sucking and holding the wafer with a chuck table through the protective member, grinding a rear face of the wafer, and exposing the mold resin embedded in the groove; forming a division starting point 25 along the division schedule line in the center of the resin exposed to the rear face; and mounting the wafer on a base 40 having flexibility, imparting an external force from the surface side, and dividing the wafer into individual device chips having the outer periphery surrounded by the resin.SELECTED DRAWING: Figure 9
【課題】ＷＬ−ＣＳＰウエーハから品質の良いデバイスチップを生成することのできるウエーハの加工方法の提供。【解決手段】格子状に形成された複数の分割予定ラインによって区画された表面の各領域にデバイスが形成されたウエーハ１１を個々のチップに分割する加工方法であって、チップの仕上がり厚さに相当する深さを有する溝１９を分割予定ラインに沿って形成する工程と、ウエーハの表面をモールド樹脂２１で被覆して溝に樹脂を埋設する工程と、ウエーハの表面に保護部材２３を配設する工程と、保護部材を介してウエーハをチャックテーブルで吸引保持し、裏面を研削して溝中に埋設された樹脂を露出させる工程と、裏面に露出した樹脂の中央に分割予定ラインに沿って分割起点２５を形成する工程と、可撓性を有する基台４０上にウエーハを載置し、表面側から外力を付与してウエーハを樹脂によって囲繞された外周を有する個々のチップに分割する工程を含む。【選択図】図９</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CLADDING OR PLATING BY SOLDERING OR WELDING ; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MACHINE TOOLS ; METAL-WORKING NOT OTHERWISE PROVIDED FOR ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SOLDERING OR UNSOLDERING ; TRANSPORTING ; WELDING ; WORKING BY LASER BEAM</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170615&DB=EPODOC&CC=JP&NR=2017107986A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170615&DB=EPODOC&CC=JP&NR=2017107986A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUGITANI TETSUKAZU</creatorcontrib><creatorcontrib>RIKU KIN</creatorcontrib><creatorcontrib>AIDA KANA</creatorcontrib><title>WAFER PROCESSING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a wafer processing method which can generate a high quality device chip from a WL-CSP wafer.SOLUTION: A wafer processing method that divides a wafer 11, on which devices are formed on each region on the surface partitioned by a plurality of division schedule lines formed in a lattice shape, into chips includes: forming a groove 19 having a depth equivalent to a finishing thickness of a chip along a division schedule line; covering a surface of a wafer with a mold resin 21 and embedding the mold resin in the groove; arranging a protective member 23 on the surface of the wafer; sucking and holding the wafer with a chuck table through the protective member, grinding a rear face of the wafer, and exposing the mold resin embedded in the groove; forming a division starting point 25 along the division schedule line in the center of the resin exposed to the rear face; and mounting the wafer on a base 40 having flexibility, imparting an external force from the surface side, and dividing the wafer into individual device chips having the outer periphery surrounded by the resin.SELECTED DRAWING: Figure 9
【課題】ＷＬ−ＣＳＰウエーハから品質の良いデバイスチップを生成することのできるウエーハの加工方法の提供。【解決手段】格子状に形成された複数の分割予定ラインによって区画された表面の各領域にデバイスが形成されたウエーハ１１を個々のチップに分割する加工方法であって、チップの仕上がり厚さに相当する深さを有する溝１９を分割予定ラインに沿って形成する工程と、ウエーハの表面をモールド樹脂２１で被覆して溝に樹脂を埋設する工程と、ウエーハの表面に保護部材２３を配設する工程と、保護部材を介してウエーハをチャックテーブルで吸引保持し、裏面を研削して溝中に埋設された樹脂を露出させる工程と、裏面に露出した樹脂の中央に分割予定ラインに沿って分割起点２５を形成する工程と、可撓性を有する基台４０上にウエーハを載置し、表面側から外力を付与してウエーハを樹脂によって囲繞された外周を有する個々のチップに分割する工程を含む。【選択図】図９</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CLADDING OR PLATING BY SOLDERING OR WELDING</subject><subject>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MACHINE TOOLS</subject><subject>METAL-WORKING NOT OTHERWISE PROVIDED FOR</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SOLDERING OR UNSOLDERING</subject><subject>TRANSPORTING</subject><subject>WELDING</subject><subject>WORKING BY LASER BEAM</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAPd3RzDVIICPJ3dg0O9vRzV_B1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhuaGBuaWFmaOxkQpAgAWdR_3</recordid><startdate>20170615</startdate><enddate>20170615</enddate><creator>SUGITANI TETSUKAZU</creator><creator>RIKU KIN</creator><creator>AIDA KANA</creator><scope>EVB</scope></search><sort><creationdate>20170615</creationdate><title>WAFER PROCESSING METHOD</title><author>SUGITANI TETSUKAZU ; RIKU KIN ; AIDA KANA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2017107986A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CLADDING OR PLATING BY SOLDERING OR WELDING</topic><topic>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MACHINE TOOLS</topic><topic>METAL-WORKING NOT OTHERWISE PROVIDED FOR</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SOLDERING OR UNSOLDERING</topic><topic>TRANSPORTING</topic><topic>WELDING</topic><topic>WORKING BY LASER BEAM</topic><toplevel>online_resources</toplevel><creatorcontrib>SUGITANI TETSUKAZU</creatorcontrib><creatorcontrib>RIKU KIN</creatorcontrib><creatorcontrib>AIDA KANA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUGITANI TETSUKAZU</au><au>RIKU KIN</au><au>AIDA KANA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WAFER PROCESSING METHOD</title><date>2017-06-15</date><risdate>2017</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wafer processing method which can generate a high quality device chip from a WL-CSP wafer.SOLUTION: A wafer processing method that divides a wafer 11, on which devices are formed on each region on the surface partitioned by a plurality of division schedule lines formed in a lattice shape, into chips includes: forming a groove 19 having a depth equivalent to a finishing thickness of a chip along a division schedule line; covering a surface of a wafer with a mold resin 21 and embedding the mold resin in the groove; arranging a protective member 23 on the surface of the wafer; sucking and holding the wafer with a chuck table through the protective member, grinding a rear face of the wafer, and exposing the mold resin embedded in the groove; forming a division starting point 25 along the division schedule line in the center of the resin exposed to the rear face; and mounting the wafer on a base 40 having flexibility, imparting an external force from the surface side, and dividing the wafer into individual device chips having the outer periphery surrounded by the resin.SELECTED DRAWING: Figure 9
【課題】ＷＬ−ＣＳＰウエーハから品質の良いデバイスチップを生成することのできるウエーハの加工方法の提供。【解決手段】格子状に形成された複数の分割予定ラインによって区画された表面の各領域にデバイスが形成されたウエーハ１１を個々のチップに分割する加工方法であって、チップの仕上がり厚さに相当する深さを有する溝１９を分割予定ラインに沿って形成する工程と、ウエーハの表面をモールド樹脂２１で被覆して溝に樹脂を埋設する工程と、ウエーハの表面に保護部材２３を配設する工程と、保護部材を介してウエーハをチャックテーブルで吸引保持し、裏面を研削して溝中に埋設された樹脂を露出させる工程と、裏面に露出した樹脂の中央に分割予定ラインに沿って分割起点２５を形成する工程と、可撓性を有する基台４０上にウエーハを載置し、表面側から外力を付与してウエーハを樹脂によって囲繞された外周を有する個々のチップに分割する工程を含む。【選択図】図９</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR PERFORMING OPERATIONS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM |
| title | WAFER PROCESSING METHOD |
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