THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of reducing parasitic capacitance.SOLUTION: The thin-film transistor includes: an oxide semiconductor layer including a channel region and low-resistance regions having lower electrical resistance than the channel region; a gate insulat...
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creator | MAKITA ATSUYA MURAI ATSUTO |
description | PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of reducing parasitic capacitance.SOLUTION: The thin-film transistor includes: an oxide semiconductor layer including a channel region and low-resistance regions having lower electrical resistance than the channel region; a gate insulating film formed on the oxide semiconductor layer; a gate electrode arranged on the gate insulating film so as to face the channel region of the oxide semiconductor layer; and source/drain electrodes electrically connected to the low-resistance regions of the oxide semiconductor layer. The gate electrode has a first electrode layer and a second electrode layer in order from the gate insulating film side. A first width of the first electrode layer along a channel length direction is larger than a second width of the second electrode layer along the channel length direction.SELECTED DRAWING: Figure 1
【課題】寄生容量を低減することが可能な薄膜トランジスタを提供する。【解決手段】薄膜トランジスタは、チャネル領域と、チャネル領域よりも電気抵抗の低い低抵抗領域とを含む酸化物半導体層と、酸化物半導体層上に形成されたゲート絶縁膜と、ゲート絶縁膜上に、酸化物半導体層のチャネル領域に対向して配置されたゲート電極と、酸化物半導体層の低抵抗領域と電気的に接続されたソース・ドレイン電極とを備える。ゲート電極は、ゲート絶縁膜の側から順に、第1の電極層と、第2の電極層とを有し、第1の電極層のチャネル長方向に沿った第1の幅は、第2の電極層のチャネル長方向に沿った第2の幅よりも大きいものである。【選択図】図1 |
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【課題】寄生容量を低減することが可能な薄膜トランジスタを提供する。【解決手段】薄膜トランジスタは、チャネル領域と、チャネル領域よりも電気抵抗の低い低抵抗領域とを含む酸化物半導体層と、酸化物半導体層上に形成されたゲート絶縁膜と、ゲート絶縁膜上に、酸化物半導体層のチャネル領域に対向して配置されたゲート電極と、酸化物半導体層の低抵抗領域と電気的に接続されたソース・ドレイン電極とを備える。ゲート電極は、ゲート絶縁膜の側から順に、第1の電極層と、第2の電極層とを有し、第1の電極層のチャネル長方向に沿った第1の幅は、第2の電極層のチャネル長方向に沿った第2の幅よりも大きいものである。【選択図】図1</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170223&DB=EPODOC&CC=JP&NR=2017041596A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170223&DB=EPODOC&CC=JP&NR=2017041596A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAKITA ATSUYA</creatorcontrib><creatorcontrib>MURAI ATSUTO</creatorcontrib><title>THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS</title><description>PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of reducing parasitic capacitance.SOLUTION: The thin-film transistor includes: an oxide semiconductor layer including a channel region and low-resistance regions having lower electrical resistance than the channel region; a gate insulating film formed on the oxide semiconductor layer; a gate electrode arranged on the gate insulating film so as to face the channel region of the oxide semiconductor layer; and source/drain electrodes electrically connected to the low-resistance regions of the oxide semiconductor layer. The gate electrode has a first electrode layer and a second electrode layer in order from the gate insulating film side. A first width of the first electrode layer along a channel length direction is larger than a second width of the second electrode layer along the channel length direction.SELECTED DRAWING: Figure 1
【課題】寄生容量を低減することが可能な薄膜トランジスタを提供する。【解決手段】薄膜トランジスタは、チャネル領域と、チャネル領域よりも電気抵抗の低い低抵抗領域とを含む酸化物半導体層と、酸化物半導体層上に形成されたゲート絶縁膜と、ゲート絶縁膜上に、酸化物半導体層のチャネル領域に対向して配置されたゲート電極と、酸化物半導体層の低抵抗領域と電気的に接続されたソース・ドレイン電極とを備える。ゲート電極は、ゲート絶縁膜の側から順に、第1の電極層と、第2の電極層とを有し、第1の電極層のチャネル長方向に沿った第1の幅は、第2の電極層のチャネル長方向に沿った第2の幅よりも大きいものである。【選択図】図1</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAJ8fD003Xz9PFVCAly9Av2DA7xD9JRCHb19XT293MJdQZyFVxcwzydXXUUHP1cFFx9XJ1Dgvz9PJ0VHAMCHIMcQ0KDeRhY0xJzilN5oTQ3g5Kba4izh25qQX58anFBYnJqXmpJvFeAkYGhuYGJoamlmaMxUYoAvv0sWQ</recordid><startdate>20170223</startdate><enddate>20170223</enddate><creator>MAKITA ATSUYA</creator><creator>MURAI ATSUTO</creator><scope>EVB</scope></search><sort><creationdate>20170223</creationdate><title>THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS</title><author>MAKITA ATSUYA ; MURAI ATSUTO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2017041596A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MAKITA ATSUYA</creatorcontrib><creatorcontrib>MURAI ATSUTO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAKITA ATSUYA</au><au>MURAI ATSUTO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS</title><date>2017-02-23</date><risdate>2017</risdate><abstract>PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of reducing parasitic capacitance.SOLUTION: The thin-film transistor includes: an oxide semiconductor layer including a channel region and low-resistance regions having lower electrical resistance than the channel region; a gate insulating film formed on the oxide semiconductor layer; a gate electrode arranged on the gate insulating film so as to face the channel region of the oxide semiconductor layer; and source/drain electrodes electrically connected to the low-resistance regions of the oxide semiconductor layer. The gate electrode has a first electrode layer and a second electrode layer in order from the gate insulating film side. A first width of the first electrode layer along a channel length direction is larger than a second width of the second electrode layer along the channel length direction.SELECTED DRAWING: Figure 1
【課題】寄生容量を低減することが可能な薄膜トランジスタを提供する。【解決手段】薄膜トランジスタは、チャネル領域と、チャネル領域よりも電気抵抗の低い低抵抗領域とを含む酸化物半導体層と、酸化物半導体層上に形成されたゲート絶縁膜と、ゲート絶縁膜上に、酸化物半導体層のチャネル領域に対向して配置されたゲート電極と、酸化物半導体層の低抵抗領域と電気的に接続されたソース・ドレイン電極とを備える。ゲート電極は、ゲート絶縁膜の側から順に、第1の電極層と、第2の電極層とを有し、第1の電極層のチャネル長方向に沿った第1の幅は、第2の電極層のチャネル長方向に沿った第2の幅よりも大きいものである。【選択図】図1</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS |
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