VERIFICATION DEVICE, METHOD, AND PROGRAM
PROBLEM TO BE SOLVED: To provide a verification device, a method, and a program that can efficiently reduce the time for verification of a semiconductor integrated circuit.SOLUTION: The verification device according to the present invention generates a net list of a non-synchronous circuit from a ne...
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| creator | ICHIMURA SHUJI |
| description | PROBLEM TO BE SOLVED: To provide a verification device, a method, and a program that can efficiently reduce the time for verification of a semiconductor integrated circuit.SOLUTION: The verification device according to the present invention generates a net list of a non-synchronous circuit from a net list of a semiconductor integrated circuit to be verified, and executes a gate-level simulation on a non-synchronous circuit indicated by the non-synchronous net list. The verification device extracts an input value and an output value of a register of the semiconductor integrated circuit and non-synchronous pass information, from the RTL descriptions of the semiconductor integrated circuit to be verified, and extracts an input value and an output value of the pass indicated by the non-synchronous pass information. The verification device executes a gate-level simulation based on an input value and an output value of the pass indicated by the non-synchronous pass information.SELECTED DRAWING: Figure 1
【課題】半導体集積回路の検証時間を効果的に削減可能な検証装置、方法およびプログラムを提供すること。【解決手段】本発明の検証装置は、検証対象の半導体集積回路のネットリストから非同期回路のネットリストを生成し、当該非同期ネットリストが示す非同期回路についてゲートレベルのシミュレーションを実行する。検証装置は、検証対象の半導体集積回路のＲＴＬ記述から半導体集積回路の備えるレジスタの入力値および出力値と、非同期パス情報とを抽出し、当該非同期パス情報が示すパスの入力値および出力値を抽出する。検証装置は、非同期パス情報が示すパスの入力値および出力値に基づいてゲートレベルのシミュレーションを実行する。【選択図】図１ |
| format | Patent |
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【課題】半導体集積回路の検証時間を効果的に削減可能な検証装置、方法およびプログラムを提供すること。【解決手段】本発明の検証装置は、検証対象の半導体集積回路のネットリストから非同期回路のネットリストを生成し、当該非同期ネットリストが示す非同期回路についてゲートレベルのシミュレーションを実行する。検証装置は、検証対象の半導体集積回路のＲＴＬ記述から半導体集積回路の備えるレジスタの入力値および出力値と、非同期パス情報とを抽出し、当該非同期パス情報が示すパスの入力値および出力値を抽出する。検証装置は、非同期パス情報が示すパスの入力値および出力値に基づいてゲートレベルのシミュレーションを実行する。【選択図】図１</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160905&DB=EPODOC&CC=JP&NR=2016162280A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160905&DB=EPODOC&CC=JP&NR=2016162280A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ICHIMURA SHUJI</creatorcontrib><title>VERIFICATION DEVICE, METHOD, AND PROGRAM</title><description>PROBLEM TO BE SOLVED: To provide a verification device, a method, and a program that can efficiently reduce the time for verification of a semiconductor integrated circuit.SOLUTION: The verification device according to the present invention generates a net list of a non-synchronous circuit from a net list of a semiconductor integrated circuit to be verified, and executes a gate-level simulation on a non-synchronous circuit indicated by the non-synchronous net list. The verification device extracts an input value and an output value of a register of the semiconductor integrated circuit and non-synchronous pass information, from the RTL descriptions of the semiconductor integrated circuit to be verified, and extracts an input value and an output value of the pass indicated by the non-synchronous pass information. The verification device executes a gate-level simulation based on an input value and an output value of the pass indicated by the non-synchronous pass information.SELECTED DRAWING: Figure 1
【課題】半導体集積回路の検証時間を効果的に削減可能な検証装置、方法およびプログラムを提供すること。【解決手段】本発明の検証装置は、検証対象の半導体集積回路のネットリストから非同期回路のネットリストを生成し、当該非同期ネットリストが示す非同期回路についてゲートレベルのシミュレーションを実行する。検証装置は、検証対象の半導体集積回路のＲＴＬ記述から半導体集積回路の備えるレジスタの入力値および出力値と、非同期パス情報とを抽出し、当該非同期パス情報が示すパスの入力値および出力値を抽出する。検証装置は、非同期パス情報が示すパスの入力値および出力値に基づいてゲートレベルのシミュレーションを実行する。【選択図】図１</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAIcw3ydPN0dgzx9PdTcHEN83R21VHwdQ3x8HfRUXD0c1EICPJ3D3L05WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGZoZmRkYWBo7GRCkCADBWJDI</recordid><startdate>20160905</startdate><enddate>20160905</enddate><creator>ICHIMURA SHUJI</creator><scope>EVB</scope></search><sort><creationdate>20160905</creationdate><title>VERIFICATION DEVICE, METHOD, AND PROGRAM</title><author>ICHIMURA SHUJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2016162280A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ICHIMURA SHUJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ICHIMURA SHUJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VERIFICATION DEVICE, METHOD, AND PROGRAM</title><date>2016-09-05</date><risdate>2016</risdate><abstract>PROBLEM TO BE SOLVED: To provide a verification device, a method, and a program that can efficiently reduce the time for verification of a semiconductor integrated circuit.SOLUTION: The verification device according to the present invention generates a net list of a non-synchronous circuit from a net list of a semiconductor integrated circuit to be verified, and executes a gate-level simulation on a non-synchronous circuit indicated by the non-synchronous net list. The verification device extracts an input value and an output value of a register of the semiconductor integrated circuit and non-synchronous pass information, from the RTL descriptions of the semiconductor integrated circuit to be verified, and extracts an input value and an output value of the pass indicated by the non-synchronous pass information. The verification device executes a gate-level simulation based on an input value and an output value of the pass indicated by the non-synchronous pass information.SELECTED DRAWING: Figure 1
【課題】半導体集積回路の検証時間を効果的に削減可能な検証装置、方法およびプログラムを提供すること。【解決手段】本発明の検証装置は、検証対象の半導体集積回路のネットリストから非同期回路のネットリストを生成し、当該非同期ネットリストが示す非同期回路についてゲートレベルのシミュレーションを実行する。検証装置は、検証対象の半導体集積回路のＲＴＬ記述から半導体集積回路の備えるレジスタの入力値および出力値と、非同期パス情報とを抽出し、当該非同期パス情報が示すパスの入力値および出力値を抽出する。検証装置は、非同期パス情報が示すパスの入力値および出力値に基づいてゲートレベルのシミュレーションを実行する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | VERIFICATION DEVICE, METHOD, AND PROGRAM |
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