SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a semiconductor device including an SOI substrate, which has a long creepage distance on a top edge side of an opening formed in an active layer without an increase in size to achieve improved withstand voltage.SOLUTION: A semiconductor device 100 comprises: an SOI s...
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creator | KANEHARA HIROMICHI |
description | PROBLEM TO BE SOLVED: To provide a semiconductor device including an SOI substrate, which has a long creepage distance on a top edge side of an opening formed in an active layer without an increase in size to achieve improved withstand voltage.SOLUTION: A semiconductor device 100 comprises: an SOI substrate 10 in which a support substrate 12, an embedded insulation layer 14 and an active layer 16 are laminated; a first insulation film 20; a second insulation film 30; an interlayer insulation film 40; a trench 50 which pierces the second insulation film 30, the first insulation film 20 and the active layer 16 and has a cavity inside and has a top edge blocked by the interlayer insulation film 40; and a first side etching region 52 which is provided in the first insulation film 20 and lies adjacent to the trench 50 and has a cavity inside, which contacts the cavity inside the trench 50. The second insulation film 30 has an etching selectivity higher than that of the first insulation film 20. An opening width W1 of the first insulation film 20 is wider than an opening width Wa of the active layer 16 and wider than an opening width W2 of the second insulation film 30.SELECTED DRAWING: Figure 1
【課題】SOI基板を備える半導体装置であって、大型化することなく、活性層に設けられた開口部の上端側の沿面距離が長く、絶縁耐圧が向上した半導体装置を提供する。【解決手段】支持基板12、埋込絶縁層14および活性層16が積層されているSOI基板10と、第1の絶縁膜20と、第2の絶縁膜30と、層間絶縁膜40と、第2の絶縁膜30、第1の絶縁膜20および活性層16を貫通し、内部に空洞を有し、層間絶縁膜40によって上端部が閉塞されているトレンチ50と、第1の絶縁膜20に設けられ、トレンチ50と隣接し、内部にトレンチ50内部の空洞と接する空洞を有する第1のサイドエッチング領域52と、を備える半導体装置100であって、第2の絶縁膜30は第1の絶縁膜20に対してエッチング選択比が高く、第1の絶縁膜20の開口幅W1が、活性層16の開口幅Waよりも広く、且つ第2の絶縁膜30の開口幅W2よりも広いことを特徴とする。【選択図】図1 |
format | Patent |
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【課題】SOI基板を備える半導体装置であって、大型化することなく、活性層に設けられた開口部の上端側の沿面距離が長く、絶縁耐圧が向上した半導体装置を提供する。【解決手段】支持基板12、埋込絶縁層14および活性層16が積層されているSOI基板10と、第1の絶縁膜20と、第2の絶縁膜30と、層間絶縁膜40と、第2の絶縁膜30、第1の絶縁膜20および活性層16を貫通し、内部に空洞を有し、層間絶縁膜40によって上端部が閉塞されているトレンチ50と、第1の絶縁膜20に設けられ、トレンチ50と隣接し、内部にトレンチ50内部の空洞と接する空洞を有する第1のサイドエッチング領域52と、を備える半導体装置100であって、第2の絶縁膜30は第1の絶縁膜20に対してエッチング選択比が高く、第1の絶縁膜20の開口幅W1が、活性層16の開口幅Waよりも広く、且つ第2の絶縁膜30の開口幅W2よりも広いことを特徴とする。【選択図】図1</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160804&DB=EPODOC&CC=JP&NR=2016139693A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160804&DB=EPODOC&CC=JP&NR=2016139693A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KANEHARA HIROMICHI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor device including an SOI substrate, which has a long creepage distance on a top edge side of an opening formed in an active layer without an increase in size to achieve improved withstand voltage.SOLUTION: A semiconductor device 100 comprises: an SOI substrate 10 in which a support substrate 12, an embedded insulation layer 14 and an active layer 16 are laminated; a first insulation film 20; a second insulation film 30; an interlayer insulation film 40; a trench 50 which pierces the second insulation film 30, the first insulation film 20 and the active layer 16 and has a cavity inside and has a top edge blocked by the interlayer insulation film 40; and a first side etching region 52 which is provided in the first insulation film 20 and lies adjacent to the trench 50 and has a cavity inside, which contacts the cavity inside the trench 50. The second insulation film 30 has an etching selectivity higher than that of the first insulation film 20. An opening width W1 of the first insulation film 20 is wider than an opening width Wa of the active layer 16 and wider than an opening width W2 of the second insulation film 30.SELECTED DRAWING: Figure 1
【課題】SOI基板を備える半導体装置であって、大型化することなく、活性層に設けられた開口部の上端側の沿面距離が長く、絶縁耐圧が向上した半導体装置を提供する。【解決手段】支持基板12、埋込絶縁層14および活性層16が積層されているSOI基板10と、第1の絶縁膜20と、第2の絶縁膜30と、層間絶縁膜40と、第2の絶縁膜30、第1の絶縁膜20および活性層16を貫通し、内部に空洞を有し、層間絶縁膜40によって上端部が閉塞されているトレンチ50と、第1の絶縁膜20に設けられ、トレンチ50と隣接し、内部にトレンチ50内部の空洞と接する空洞を有する第1のサイドエッチング領域52と、を備える半導体装置100であって、第2の絶縁膜30は第1の絶縁膜20に対してエッチング選択比が高く、第1の絶縁膜20の開口幅W1が、活性層16の開口幅Waよりも広く、且つ第2の絶縁膜30の開口幅W2よりも広いことを特徴とする。【選択図】図1</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhmaGxpZmlsaOxkQpAgC-8h8u</recordid><startdate>20160804</startdate><enddate>20160804</enddate><creator>KANEHARA HIROMICHI</creator><scope>EVB</scope></search><sort><creationdate>20160804</creationdate><title>SEMICONDUCTOR DEVICE</title><author>KANEHARA HIROMICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2016139693A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KANEHARA HIROMICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KANEHARA HIROMICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2016-08-04</date><risdate>2016</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor device including an SOI substrate, which has a long creepage distance on a top edge side of an opening formed in an active layer without an increase in size to achieve improved withstand voltage.SOLUTION: A semiconductor device 100 comprises: an SOI substrate 10 in which a support substrate 12, an embedded insulation layer 14 and an active layer 16 are laminated; a first insulation film 20; a second insulation film 30; an interlayer insulation film 40; a trench 50 which pierces the second insulation film 30, the first insulation film 20 and the active layer 16 and has a cavity inside and has a top edge blocked by the interlayer insulation film 40; and a first side etching region 52 which is provided in the first insulation film 20 and lies adjacent to the trench 50 and has a cavity inside, which contacts the cavity inside the trench 50. The second insulation film 30 has an etching selectivity higher than that of the first insulation film 20. An opening width W1 of the first insulation film 20 is wider than an opening width Wa of the active layer 16 and wider than an opening width W2 of the second insulation film 30.SELECTED DRAWING: Figure 1
【課題】SOI基板を備える半導体装置であって、大型化することなく、活性層に設けられた開口部の上端側の沿面距離が長く、絶縁耐圧が向上した半導体装置を提供する。【解決手段】支持基板12、埋込絶縁層14および活性層16が積層されているSOI基板10と、第1の絶縁膜20と、第2の絶縁膜30と、層間絶縁膜40と、第2の絶縁膜30、第1の絶縁膜20および活性層16を貫通し、内部に空洞を有し、層間絶縁膜40によって上端部が閉塞されているトレンチ50と、第1の絶縁膜20に設けられ、トレンチ50と隣接し、内部にトレンチ50内部の空洞と接する空洞を有する第1のサイドエッチング領域52と、を備える半導体装置100であって、第2の絶縁膜30は第1の絶縁膜20に対してエッチング選択比が高く、第1の絶縁膜20の開口幅W1が、活性層16の開口幅Waよりも広く、且つ第2の絶縁膜30の開口幅W2よりも広いことを特徴とする。【選択図】図1</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE |
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