SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD

PROBLEM TO BE SOLVED: To provide a silicon substrate processing method capable of achieving high depth accuracy of a first recess regarding a structure where the first recess is processed from the surface side of a silicon substrate, and then a second recess is processed from the rear side of the su...

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description PROBLEM TO BE SOLVED: To provide a silicon substrate processing method capable of achieving high depth accuracy of a first recess regarding a structure where the first recess is processed from the surface side of a silicon substrate, and then a second recess is processed from the rear side of the substrate to be communicated with the first recess.SOLUTION: A first recess 111 is processed on the first surface of a silicon substrate 101, and a side wall protection film 112S is formed in the side wall of the first recess 111. Then, after etching of the bottom part of the first recess 111, a cavity 113 larger than the first recess 111 regarding a sectional area in a direction parallel to a substrate surface is formed, and an etching stop film 114 is formed in the inner wall of the cavity 113. Then, a second recess 117 is formed from the second surface of the silicon substrate 101 to expose at least a part of the etching stop film 114. Lastly, the etching stop film 114 is removed to communicate the first recess 111 and the second recess 117 with each other, thereby forming a through-hole.SELECTED DRAWING: Figure 4 【課題】シリコン基板の表面側から第一の窪みを加工し、次いで基板裏面側から第二の窪みを加工して第一の窪みと連通させた構造体について、第一の窪みの深さ精度が良好なシリコン基板の加工方法を提供する。【解決手段】シリコン基板101の第一の面に第一の窪み111を加工し、第一の窪み111の側壁に側壁保護膜112Sを形成する。次いで、第一の窪み111の底部をエッチングした後、基板面に平行な方向の断面積に関して第一の窪み111よりも大きい空洞113を形成し、空洞113内壁にエッチングストップ膜114を形成する。次いで、シリコン基板101の第二面から第二の窪み117を加工し、エッチングストップ膜114の少なくとも一部を露出させる。最後に、エッチングストップ膜114を除去して、第一の窪み111と第二の窪み117とを連通させることにより貫通孔を形成する。【選択図】図4
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2016117174A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2016117174A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2016117174A3</originalsourceid><addsrcrecordid>eNrjZLAN9vTxdPb3UwgOdQoOCXIMcVUICPJ3dg0O9vRzV_B1DfHwd1Fw9HNR8PEMDPV0UXDxDHb2cAxyd1XwcHV04WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGZoaG5obmJo7GRCkCAIa_Kjc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD</title><source>esp@cenet</source><creator>FUKUMOTO TAKAYUKI</creator><creatorcontrib>FUKUMOTO TAKAYUKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a silicon substrate processing method capable of achieving high depth accuracy of a first recess regarding a structure where the first recess is processed from the surface side of a silicon substrate, and then a second recess is processed from the rear side of the substrate to be communicated with the first recess.SOLUTION: A first recess 111 is processed on the first surface of a silicon substrate 101, and a side wall protection film 112S is formed in the side wall of the first recess 111. Then, after etching of the bottom part of the first recess 111, a cavity 113 larger than the first recess 111 regarding a sectional area in a direction parallel to a substrate surface is formed, and an etching stop film 114 is formed in the inner wall of the cavity 113. Then, a second recess 117 is formed from the second surface of the silicon substrate 101 to expose at least a part of the etching stop film 114. Lastly, the etching stop film 114 is removed to communicate the first recess 111 and the second recess 117 with each other, thereby forming a through-hole.SELECTED DRAWING: Figure 4 【課題】シリコン基板の表面側から第一の窪みを加工し、次いで基板裏面側から第二の窪みを加工して第一の窪みと連通させた構造体について、第一の窪みの深さ精度が良好なシリコン基板の加工方法を提供する。【解決手段】シリコン基板101の第一の面に第一の窪み111を加工し、第一の窪み111の側壁に側壁保護膜112Sを形成する。次いで、第一の窪み111の底部をエッチングした後、基板面に平行な方向の断面積に関して第一の窪み111よりも大きい空洞113を形成し、空洞113内壁にエッチングストップ膜114を形成する。次いで、シリコン基板101の第二面から第二の窪み117を加工し、エッチングストップ膜114の少なくとも一部を露出させる。最後に、エッチングストップ膜114を除去して、第一の窪み111と第二の窪み117とを連通させることにより貫通孔を形成する。【選択図】図4</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CORRECTION OF TYPOGRAPHICAL ERRORS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME ; LINING MACHINES ; PERFORMING OPERATIONS ; PRINTING ; SELECTIVE PRINTING MECHANISMS ; SEMICONDUCTOR DEVICES ; STAMPS ; TRANSPORTING ; TYPEWRITERS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2016117174A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2016117174A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FUKUMOTO TAKAYUKI</creatorcontrib><title>SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD</title><description>PROBLEM TO BE SOLVED: To provide a silicon substrate processing method capable of achieving high depth accuracy of a first recess regarding a structure where the first recess is processed from the surface side of a silicon substrate, and then a second recess is processed from the rear side of the substrate to be communicated with the first recess.SOLUTION: A first recess 111 is processed on the first surface of a silicon substrate 101, and a side wall protection film 112S is formed in the side wall of the first recess 111. Then, after etching of the bottom part of the first recess 111, a cavity 113 larger than the first recess 111 regarding a sectional area in a direction parallel to a substrate surface is formed, and an etching stop film 114 is formed in the inner wall of the cavity 113. Then, a second recess 117 is formed from the second surface of the silicon substrate 101 to expose at least a part of the etching stop film 114. Lastly, the etching stop film 114 is removed to communicate the first recess 111 and the second recess 117 with each other, thereby forming a through-hole.SELECTED DRAWING: Figure 4 【課題】シリコン基板の表面側から第一の窪みを加工し、次いで基板裏面側から第二の窪みを加工して第一の窪みと連通させた構造体について、第一の窪みの深さ精度が良好なシリコン基板の加工方法を提供する。【解決手段】シリコン基板101の第一の面に第一の窪み111を加工し、第一の窪み111の側壁に側壁保護膜112Sを形成する。次いで、第一の窪み111の底部をエッチングした後、基板面に平行な方向の断面積に関して第一の窪み111よりも大きい空洞113を形成し、空洞113内壁にエッチングストップ膜114を形成する。次いで、シリコン基板101の第二面から第二の窪み117を加工し、エッチングストップ膜114の少なくとも一部を露出させる。最後に、エッチングストップ膜114を除去して、第一の窪み111と第二の窪み117とを連通させることにより貫通孔を形成する。【選択図】図4</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CORRECTION OF TYPOGRAPHICAL ERRORS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME</subject><subject>LINING MACHINES</subject><subject>PERFORMING OPERATIONS</subject><subject>PRINTING</subject><subject>SELECTIVE PRINTING MECHANISMS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STAMPS</subject><subject>TRANSPORTING</subject><subject>TYPEWRITERS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAN9vTxdPb3UwgOdQoOCXIMcVUICPJ3dg0O9vRzV_B1DfHwd1Fw9HNR8PEMDPV0UXDxDHb2cAxyd1XwcHV04WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGZoaG5obmJo7GRCkCAIa_Kjc</recordid><startdate>20160630</startdate><enddate>20160630</enddate><creator>FUKUMOTO TAKAYUKI</creator><scope>EVB</scope></search><sort><creationdate>20160630</creationdate><title>SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD</title><author>FUKUMOTO TAKAYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2016117174A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CORRECTION OF TYPOGRAPHICAL ERRORS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME</topic><topic>LINING MACHINES</topic><topic>PERFORMING OPERATIONS</topic><topic>PRINTING</topic><topic>SELECTIVE PRINTING MECHANISMS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STAMPS</topic><topic>TRANSPORTING</topic><topic>TYPEWRITERS</topic><toplevel>online_resources</toplevel><creatorcontrib>FUKUMOTO TAKAYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FUKUMOTO TAKAYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD</title><date>2016-06-30</date><risdate>2016</risdate><abstract>PROBLEM TO BE SOLVED: To provide a silicon substrate processing method capable of achieving high depth accuracy of a first recess regarding a structure where the first recess is processed from the surface side of a silicon substrate, and then a second recess is processed from the rear side of the substrate to be communicated with the first recess.SOLUTION: A first recess 111 is processed on the first surface of a silicon substrate 101, and a side wall protection film 112S is formed in the side wall of the first recess 111. Then, after etching of the bottom part of the first recess 111, a cavity 113 larger than the first recess 111 regarding a sectional area in a direction parallel to a substrate surface is formed, and an etching stop film 114 is formed in the inner wall of the cavity 113. Then, a second recess 117 is formed from the second surface of the silicon substrate 101 to expose at least a part of the etching stop film 114. Lastly, the etching stop film 114 is removed to communicate the first recess 111 and the second recess 117 with each other, thereby forming a through-hole.SELECTED DRAWING: Figure 4 【課題】シリコン基板の表面側から第一の窪みを加工し、次いで基板裏面側から第二の窪みを加工して第一の窪みと連通させた構造体について、第一の窪みの深さ精度が良好なシリコン基板の加工方法を提供する。【解決手段】シリコン基板101の第一の面に第一の窪み111を加工し、第一の窪み111の側壁に側壁保護膜112Sを形成する。次いで、第一の窪み111の底部をエッチングした後、基板面に平行な方向の断面積に関して第一の窪み111よりも大きい空洞113を形成し、空洞113内壁にエッチングストップ膜114を形成する。次いで、シリコン基板101の第二面から第二の窪み117を加工し、エッチングストップ膜114の少なくとも一部を露出させる。最後に、エッチングストップ膜114を除去して、第一の窪み111と第二の窪み117とを連通させることにより貫通孔を形成する。【選択図】図4</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CORRECTION OF TYPOGRAPHICAL ERRORS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME
LINING MACHINES
PERFORMING OPERATIONS
PRINTING
SELECTIVE PRINTING MECHANISMS
SEMICONDUCTOR DEVICES
STAMPS
TRANSPORTING
TYPEWRITERS
title SILICON SUBSTRATE PROCESSING METHOD AND LIQUID DISCHARGE HEAD
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