WIRING BOARD AND MANUFACTURING METHOD THEREOF

WIRING BOARD AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer.SOLUTION: The wiring board comprises a base wiring board 2 and a re-wiring part 3. The base wiring board 2 includes: a wiring layer 21; an insulating laye...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MUTSUKAWA AKIO, KANEDA WATARU, SHIMIZU NORIYOSHI, KOYAMA TOSHINORI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MUTSUKAWA AKIO
KANEDA WATARU
SHIMIZU NORIYOSHI
KOYAMA TOSHINORI
description PROBLEM TO BE SOLVED: To provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer.SOLUTION: The wiring board comprises a base wiring board 2 and a re-wiring part 3. The base wiring board 2 includes: a wiring layer 21; an insulating layer 31 in which the wiring layer 21 is embedded and a via hole VH1 is formed at a lower side of the wiring layer 21; and a wiring layer 22 which is formed at a lower side of the insulating layer 31 and connected to the wiring layer 21 via a via conductor within the via hole VH1. The re-wiring part 3 includes: an insulating layer 34 which is formed on the base wiring board 2 and with which a via hole VH4 is formed on the wiring layer 21; and a re-wiring layer 41 which is formed on the insulating layer 34 and connected to the wiring layer 21 via a via conductor within the via hole VH4. The re-wiring layer 41 is formed from a seed layer 41a and a metal plating layer 41b thereon, and the seed layer 41a is as wide as or wider than the metal plating layer 41b.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2014154800A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2014154800A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2014154800A3</originalsourceid><addsrcrecordid>eNrjZNAN9wzy9HNXcPJ3DHJRcPRzUfB19At1c3QOCQWL-7qGePi7KIR4uAa5-rvxMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjA0MTQ1MTCwMDR2OiFAEA_Nolxw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING BOARD AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>MUTSUKAWA AKIO ; KANEDA WATARU ; SHIMIZU NORIYOSHI ; KOYAMA TOSHINORI</creator><creatorcontrib>MUTSUKAWA AKIO ; KANEDA WATARU ; SHIMIZU NORIYOSHI ; KOYAMA TOSHINORI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer.SOLUTION: The wiring board comprises a base wiring board 2 and a re-wiring part 3. The base wiring board 2 includes: a wiring layer 21; an insulating layer 31 in which the wiring layer 21 is embedded and a via hole VH1 is formed at a lower side of the wiring layer 21; and a wiring layer 22 which is formed at a lower side of the insulating layer 31 and connected to the wiring layer 21 via a via conductor within the via hole VH1. The re-wiring part 3 includes: an insulating layer 34 which is formed on the base wiring board 2 and with which a via hole VH4 is formed on the wiring layer 21; and a re-wiring layer 41 which is formed on the insulating layer 34 and connected to the wiring layer 21 via a via conductor within the via hole VH4. The re-wiring layer 41 is formed from a seed layer 41a and a metal plating layer 41b thereon, and the seed layer 41a is as wide as or wider than the metal plating layer 41b.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140825&amp;DB=EPODOC&amp;CC=JP&amp;NR=2014154800A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140825&amp;DB=EPODOC&amp;CC=JP&amp;NR=2014154800A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MUTSUKAWA AKIO</creatorcontrib><creatorcontrib>KANEDA WATARU</creatorcontrib><creatorcontrib>SHIMIZU NORIYOSHI</creatorcontrib><creatorcontrib>KOYAMA TOSHINORI</creatorcontrib><title>WIRING BOARD AND MANUFACTURING METHOD THEREOF</title><description>PROBLEM TO BE SOLVED: To provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer.SOLUTION: The wiring board comprises a base wiring board 2 and a re-wiring part 3. The base wiring board 2 includes: a wiring layer 21; an insulating layer 31 in which the wiring layer 21 is embedded and a via hole VH1 is formed at a lower side of the wiring layer 21; and a wiring layer 22 which is formed at a lower side of the insulating layer 31 and connected to the wiring layer 21 via a via conductor within the via hole VH1. The re-wiring part 3 includes: an insulating layer 34 which is formed on the base wiring board 2 and with which a via hole VH4 is formed on the wiring layer 21; and a re-wiring layer 41 which is formed on the insulating layer 34 and connected to the wiring layer 21 via a via conductor within the via hole VH4. The re-wiring layer 41 is formed from a seed layer 41a and a metal plating layer 41b thereon, and the seed layer 41a is as wide as or wider than the metal plating layer 41b.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAN9wzy9HNXcPJ3DHJRcPRzUfB19At1c3QOCQWL-7qGePi7KIR4uAa5-rvxMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjA0MTQ1MTCwMDR2OiFAEA_Nolxw</recordid><startdate>20140825</startdate><enddate>20140825</enddate><creator>MUTSUKAWA AKIO</creator><creator>KANEDA WATARU</creator><creator>SHIMIZU NORIYOSHI</creator><creator>KOYAMA TOSHINORI</creator><scope>EVB</scope></search><sort><creationdate>20140825</creationdate><title>WIRING BOARD AND MANUFACTURING METHOD THEREOF</title><author>MUTSUKAWA AKIO ; KANEDA WATARU ; SHIMIZU NORIYOSHI ; KOYAMA TOSHINORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2014154800A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MUTSUKAWA AKIO</creatorcontrib><creatorcontrib>KANEDA WATARU</creatorcontrib><creatorcontrib>SHIMIZU NORIYOSHI</creatorcontrib><creatorcontrib>KOYAMA TOSHINORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MUTSUKAWA AKIO</au><au>KANEDA WATARU</au><au>SHIMIZU NORIYOSHI</au><au>KOYAMA TOSHINORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING BOARD AND MANUFACTURING METHOD THEREOF</title><date>2014-08-25</date><risdate>2014</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer.SOLUTION: The wiring board comprises a base wiring board 2 and a re-wiring part 3. The base wiring board 2 includes: a wiring layer 21; an insulating layer 31 in which the wiring layer 21 is embedded and a via hole VH1 is formed at a lower side of the wiring layer 21; and a wiring layer 22 which is formed at a lower side of the insulating layer 31 and connected to the wiring layer 21 via a via conductor within the via hole VH1. The re-wiring part 3 includes: an insulating layer 34 which is formed on the base wiring board 2 and with which a via hole VH4 is formed on the wiring layer 21; and a re-wiring layer 41 which is formed on the insulating layer 34 and connected to the wiring layer 21 via a via conductor within the via hole VH4. The re-wiring layer 41 is formed from a seed layer 41a and a metal plating layer 41b thereon, and the seed layer 41a is as wide as or wider than the metal plating layer 41b.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2014154800A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
title WIRING BOARD AND MANUFACTURING METHOD THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T20%3A09%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MUTSUKAWA%20AKIO&rft.date=2014-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2014154800A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true