WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD
PROBLEM TO BE SOLVED: To provide a wiring pattern formation substrate which can decrease a wiring resistance value while achieving narrowing of a wiring area.SOLUTION: A wiring pattern formation substrate comprises: a main wiring pattern 31 formed in a frame region on a surface of an insulating tran...
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| creator | HOTTA SHINJI MIYAJIMA KENTARO |
| description | PROBLEM TO BE SOLVED: To provide a wiring pattern formation substrate which can decrease a wiring resistance value while achieving narrowing of a wiring area.SOLUTION: A wiring pattern formation substrate comprises: a main wiring pattern 31 formed in a frame region on a surface of an insulating transparent base material 10 by a first printing process; an auxiliary wiring pattern 32 layered on a part of the main wiring pattern 31 in a lengthwise direction in an overlapping manner by a second printing process; a thin film pattern part 20A only of the main wiring pattern 31 provided in a partial region of a wiring pattern 20 in a lengthwise direction; and a thick film pattern part 20B provided having a thickness of the wiring pattern thicker than a thickness of the wiring pattern 20 of the thin film pattern part 20A in the other region of the wiring pattern in the lengthwise direction, in which the thick film pattern part 20B is provided at a part where a wiring resistance value increases. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2014150181A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2014150181A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2014150181A3</originalsourceid><addsrcrecordid>eNrjZHAL9wzy9HNXCHAMCXEN8lNw8w_ydQzx9PdTCA51Cg4JcgxxVXD0c1HAqczXNcTD34WHgTUtMac4lRdKczMoubmGOHvophbkx6cWFyQmp-allsR7BRgZGJoYmhoYWhg6GhOlCAA82y0a</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD</title><source>esp@cenet</source><creator>HOTTA SHINJI ; MIYAJIMA KENTARO</creator><creatorcontrib>HOTTA SHINJI ; MIYAJIMA KENTARO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wiring pattern formation substrate which can decrease a wiring resistance value while achieving narrowing of a wiring area.SOLUTION: A wiring pattern formation substrate comprises: a main wiring pattern 31 formed in a frame region on a surface of an insulating transparent base material 10 by a first printing process; an auxiliary wiring pattern 32 layered on a part of the main wiring pattern 31 in a lengthwise direction in an overlapping manner by a second printing process; a thin film pattern part 20A only of the main wiring pattern 31 provided in a partial region of a wiring pattern 20 in a lengthwise direction; and a thick film pattern part 20B provided having a thickness of the wiring pattern thicker than a thickness of the wiring pattern 20 of the thin film pattern part 20A in the other region of the wiring pattern in the lengthwise direction, in which the thick film pattern part 20B is provided at a part where a wiring resistance value increases.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140821&DB=EPODOC&CC=JP&NR=2014150181A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140821&DB=EPODOC&CC=JP&NR=2014150181A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HOTTA SHINJI</creatorcontrib><creatorcontrib>MIYAJIMA KENTARO</creatorcontrib><title>WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD</title><description>PROBLEM TO BE SOLVED: To provide a wiring pattern formation substrate which can decrease a wiring resistance value while achieving narrowing of a wiring area.SOLUTION: A wiring pattern formation substrate comprises: a main wiring pattern 31 formed in a frame region on a surface of an insulating transparent base material 10 by a first printing process; an auxiliary wiring pattern 32 layered on a part of the main wiring pattern 31 in a lengthwise direction in an overlapping manner by a second printing process; a thin film pattern part 20A only of the main wiring pattern 31 provided in a partial region of a wiring pattern 20 in a lengthwise direction; and a thick film pattern part 20B provided having a thickness of the wiring pattern thicker than a thickness of the wiring pattern 20 of the thin film pattern part 20A in the other region of the wiring pattern in the lengthwise direction, in which the thick film pattern part 20B is provided at a part where a wiring resistance value increases.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAL9wzy9HNXCHAMCXEN8lNw8w_ydQzx9PdTCA51Cg4JcgxxVXD0c1HAqczXNcTD34WHgTUtMac4lRdKczMoubmGOHvophbkx6cWFyQmp-allsR7BRgZGJoYmhoYWhg6GhOlCAA82y0a</recordid><startdate>20140821</startdate><enddate>20140821</enddate><creator>HOTTA SHINJI</creator><creator>MIYAJIMA KENTARO</creator><scope>EVB</scope></search><sort><creationdate>20140821</creationdate><title>WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD</title><author>HOTTA SHINJI ; MIYAJIMA KENTARO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2014150181A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>HOTTA SHINJI</creatorcontrib><creatorcontrib>MIYAJIMA KENTARO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HOTTA SHINJI</au><au>MIYAJIMA KENTARO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD</title><date>2014-08-21</date><risdate>2014</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wiring pattern formation substrate which can decrease a wiring resistance value while achieving narrowing of a wiring area.SOLUTION: A wiring pattern formation substrate comprises: a main wiring pattern 31 formed in a frame region on a surface of an insulating transparent base material 10 by a first printing process; an auxiliary wiring pattern 32 layered on a part of the main wiring pattern 31 in a lengthwise direction in an overlapping manner by a second printing process; a thin film pattern part 20A only of the main wiring pattern 31 provided in a partial region of a wiring pattern 20 in a lengthwise direction; and a thick film pattern part 20B provided having a thickness of the wiring pattern thicker than a thickness of the wiring pattern 20 of the thin film pattern part 20A in the other region of the wiring pattern in the lengthwise direction, in which the thick film pattern part 20B is provided at a part where a wiring resistance value increases.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
| title | WIRING PATTERN FORMATION SUBSTRATE AND WIRING PATTERN FORMATION METHOD |
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