SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device mounting structure and manufacturing method capable of preventing breakage of a semiconductor element or degradation of its characteristic, and capable of surely fitting it in place.SOLUTION: Electrode parts 11, 21 of a mounting board 1 and a s...

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Hauptverfasser: SHIRATORI YUTA, KAYAO NORIHIDE
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creator SHIRATORI YUTA
KAYAO NORIHIDE
description PROBLEM TO BE SOLVED: To provide a semiconductor device mounting structure and manufacturing method capable of preventing breakage of a semiconductor element or degradation of its characteristic, and capable of surely fitting it in place.SOLUTION: Electrode parts 11, 21 of a mounting board 1 and a semiconductor element 2 are joined together via a low melting point solder by a concave bump 16 formed on the mounting board 1 and a convex bump 27 formed on the semiconductor element 2. This allows the semiconductor element 2 to be fitted to the mounting board 1 without raising the temperature of the same or applying a high load to the same, making it possible to prevent breakage or degradation of the semiconductor element 2. Furthermore, as the low melting point solder connects a barrier layer 14 and a barrier layer 25 covering the top and the side surfaces of the other end portion of a bump post 23, the contact area of the low melting point solder is increased, so that bond strength capable of resisting thermal stresses generated by heating at bonding time, making it possible to fit the semiconductor element 2 to the mounting board 1 with greater sureness.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2014143305A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2014143305A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2014143305A3</originalsourceid><addsrcrecordid>eNrjZAgNdvX1dPb3cwl1DvEPUnBxDfN0dlXw9Q_1C_H0c1cIDgkCSoQGuSo4-rkoYFfr6Bfq5ghSBNLg6xri4e_Cw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAxNDE2MjQ1MHY2JUgQAFC4xZg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><source>esp@cenet</source><creator>SHIRATORI YUTA ; KAYAO NORIHIDE</creator><creatorcontrib>SHIRATORI YUTA ; KAYAO NORIHIDE</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a semiconductor device mounting structure and manufacturing method capable of preventing breakage of a semiconductor element or degradation of its characteristic, and capable of surely fitting it in place.SOLUTION: Electrode parts 11, 21 of a mounting board 1 and a semiconductor element 2 are joined together via a low melting point solder by a concave bump 16 formed on the mounting board 1 and a convex bump 27 formed on the semiconductor element 2. This allows the semiconductor element 2 to be fitted to the mounting board 1 without raising the temperature of the same or applying a high load to the same, making it possible to prevent breakage or degradation of the semiconductor element 2. Furthermore, as the low melting point solder connects a barrier layer 14 and a barrier layer 25 covering the top and the side surfaces of the other end portion of a bump post 23, the contact area of the low melting point solder is increased, so that bond strength capable of resisting thermal stresses generated by heating at bonding time, making it possible to fit the semiconductor element 2 to the mounting board 1 with greater sureness.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140807&amp;DB=EPODOC&amp;CC=JP&amp;NR=2014143305A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140807&amp;DB=EPODOC&amp;CC=JP&amp;NR=2014143305A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIRATORI YUTA</creatorcontrib><creatorcontrib>KAYAO NORIHIDE</creatorcontrib><title>SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor device mounting structure and manufacturing method capable of preventing breakage of a semiconductor element or degradation of its characteristic, and capable of surely fitting it in place.SOLUTION: Electrode parts 11, 21 of a mounting board 1 and a semiconductor element 2 are joined together via a low melting point solder by a concave bump 16 formed on the mounting board 1 and a convex bump 27 formed on the semiconductor element 2. This allows the semiconductor element 2 to be fitted to the mounting board 1 without raising the temperature of the same or applying a high load to the same, making it possible to prevent breakage or degradation of the semiconductor element 2. Furthermore, as the low melting point solder connects a barrier layer 14 and a barrier layer 25 covering the top and the side surfaces of the other end portion of a bump post 23, the contact area of the low melting point solder is increased, so that bond strength capable of resisting thermal stresses generated by heating at bonding time, making it possible to fit the semiconductor element 2 to the mounting board 1 with greater sureness.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgNdvX1dPb3cwl1DvEPUnBxDfN0dlXw9Q_1C_H0c1cIDgkCSoQGuSo4-rkoYFfr6Bfq5ghSBNLg6xri4e_Cw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAxNDE2MjQ1MHY2JUgQAFC4xZg</recordid><startdate>20140807</startdate><enddate>20140807</enddate><creator>SHIRATORI YUTA</creator><creator>KAYAO NORIHIDE</creator><scope>EVB</scope></search><sort><creationdate>20140807</creationdate><title>SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><author>SHIRATORI YUTA ; KAYAO NORIHIDE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2014143305A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIRATORI YUTA</creatorcontrib><creatorcontrib>KAYAO NORIHIDE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIRATORI YUTA</au><au>KAYAO NORIHIDE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><date>2014-08-07</date><risdate>2014</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor device mounting structure and manufacturing method capable of preventing breakage of a semiconductor element or degradation of its characteristic, and capable of surely fitting it in place.SOLUTION: Electrode parts 11, 21 of a mounting board 1 and a semiconductor element 2 are joined together via a low melting point solder by a concave bump 16 formed on the mounting board 1 and a convex bump 27 formed on the semiconductor element 2. This allows the semiconductor element 2 to be fitted to the mounting board 1 without raising the temperature of the same or applying a high load to the same, making it possible to prevent breakage or degradation of the semiconductor element 2. Furthermore, as the low melting point solder connects a barrier layer 14 and a barrier layer 25 covering the top and the side surfaces of the other end portion of a bump post 23, the contact area of the low melting point solder is increased, so that bond strength capable of resisting thermal stresses generated by heating at bonding time, making it possible to fit the semiconductor element 2 to the mounting board 1 with greater sureness.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T16%3A59%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHIRATORI%20YUTA&rft.date=2014-08-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2014143305A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true