PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF
PROBLEM TO BE SOLVED: To provide a package carrier suitable for locating at least one chip, and a manufacturing method thereof.SOLUTION: A support plate having an upper surface and a patterning circuit layer thereon is formed. One part of the upper surface of the support plate is exposed by the patt...
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description | PROBLEM TO BE SOLVED: To provide a package carrier suitable for locating at least one chip, and a manufacturing method thereof.SOLUTION: A support plate having an upper surface and a patterning circuit layer thereon is formed. One part of the upper surface of the support plate is exposed by the patterning circuit layer. An insulation layer, and a conductive layer provided on a first surface of the insulation layer are laminated on the patterning circuit layer. The patterning circuit layer and an exposed portion of the upper surface are covered by the insulation layer. Plural conductive connection structures are formed on the patterning circuit layer. The conductive layer is patterned, so as to define plural pads respectively connected to the conductive connection structure and expose one part of the first surface of the insulation layer. By removing the support plate, a second surface of the insulation layer is exposed. The second surface and a joint face of the patterning circuit layer are the same plane. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2013140940A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2013140940A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2013140940A3</originalsourceid><addsrcrecordid>eNrjZDAIcHT2dnR3VXB2DArydA1ScPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBobGhiYGliYGjsZEKQIAYwUmhA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>SON SEO HO</creator><creatorcontrib>SON SEO HO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a package carrier suitable for locating at least one chip, and a manufacturing method thereof.SOLUTION: A support plate having an upper surface and a patterning circuit layer thereon is formed. One part of the upper surface of the support plate is exposed by the patterning circuit layer. An insulation layer, and a conductive layer provided on a first surface of the insulation layer are laminated on the patterning circuit layer. The patterning circuit layer and an exposed portion of the upper surface are covered by the insulation layer. Plural conductive connection structures are formed on the patterning circuit layer. The conductive layer is patterned, so as to define plural pads respectively connected to the conductive connection structure and expose one part of the first surface of the insulation layer. By removing the support plate, a second surface of the insulation layer is exposed. The second surface and a joint face of the patterning circuit layer are the same plane.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130718&DB=EPODOC&CC=JP&NR=2013140940A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130718&DB=EPODOC&CC=JP&NR=2013140940A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SON SEO HO</creatorcontrib><title>PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF</title><description>PROBLEM TO BE SOLVED: To provide a package carrier suitable for locating at least one chip, and a manufacturing method thereof.SOLUTION: A support plate having an upper surface and a patterning circuit layer thereon is formed. One part of the upper surface of the support plate is exposed by the patterning circuit layer. An insulation layer, and a conductive layer provided on a first surface of the insulation layer are laminated on the patterning circuit layer. The patterning circuit layer and an exposed portion of the upper surface are covered by the insulation layer. Plural conductive connection structures are formed on the patterning circuit layer. The conductive layer is patterned, so as to define plural pads respectively connected to the conductive connection structure and expose one part of the first surface of the insulation layer. By removing the support plate, a second surface of the insulation layer is exposed. The second surface and a joint face of the patterning circuit layer are the same plane.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAIcHT2dnR3VXB2DArydA1ScPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBobGhiYGliYGjsZEKQIAYwUmhA</recordid><startdate>20130718</startdate><enddate>20130718</enddate><creator>SON SEO HO</creator><scope>EVB</scope></search><sort><creationdate>20130718</creationdate><title>PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF</title><author>SON SEO HO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2013140940A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SON SEO HO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SON SEO HO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF</title><date>2013-07-18</date><risdate>2013</risdate><abstract>PROBLEM TO BE SOLVED: To provide a package carrier suitable for locating at least one chip, and a manufacturing method thereof.SOLUTION: A support plate having an upper surface and a patterning circuit layer thereon is formed. One part of the upper surface of the support plate is exposed by the patterning circuit layer. An insulation layer, and a conductive layer provided on a first surface of the insulation layer are laminated on the patterning circuit layer. The patterning circuit layer and an exposed portion of the upper surface are covered by the insulation layer. Plural conductive connection structures are formed on the patterning circuit layer. The conductive layer is patterned, so as to define plural pads respectively connected to the conductive connection structure and expose one part of the first surface of the insulation layer. By removing the support plate, a second surface of the insulation layer is exposed. The second surface and a joint face of the patterning circuit layer are the same plane.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF |
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