ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE
PROBLEM TO BE SOLVED: To provide an electronic component built-in substrate having a new structure that deals with the thickness reduction when the electronic component built-in substrate is laminated.SOLUTION: An electronic component built-in substrate 1 includes: a wiring layer 50; an electronic c...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | ISHIZUKI YOSHIKATSU |
| description | PROBLEM TO BE SOLVED: To provide an electronic component built-in substrate having a new structure that deals with the thickness reduction when the electronic component built-in substrate is laminated.SOLUTION: An electronic component built-in substrate 1 includes: a wiring layer 50; an electronic component 30 electrically connected with the wiring layer 50; a first electrode 20 provided on the wiring layer 50 and electrically connected with the wiring layer 50; a metal joint material 22 provided on the first electrode 20; a second electrode 56 provided below the wiring layer 50 and protruding downward from the wiring layer; and an insulation part 40 where the electronic component 30, the first electrode 20, and the metal joint material 22 are embedded. When the electronic component built-in substrate 1 is laminated on another electronic component built-in substrate 1, the second electrode 56 is embedded in the metal joint material 22 to be joined thereto. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2013138080A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2013138080A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2013138080A3</originalsourceid><addsrcrecordid>eNqNjLEOgjAQQFkcjPoPF2dJiiysRzmkhl6bch2cCDF1MkqCv-R_uvgBTG95722zL_WkJTg2GrSz3jGxQB1NL7lhGGI9SEChE1jk2KKWGAxfwJJ0rgHXwuoBcgM9WsMoxjHIzdPaeJ9tHtNzSYc_d9mxJdFdnub3mJZ5uqdX-oxXf1ZFWZSVqhSWq6Qf21tHaw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE</title><source>esp@cenet</source><creator>ISHIZUKI YOSHIKATSU</creator><creatorcontrib>ISHIZUKI YOSHIKATSU</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide an electronic component built-in substrate having a new structure that deals with the thickness reduction when the electronic component built-in substrate is laminated.SOLUTION: An electronic component built-in substrate 1 includes: a wiring layer 50; an electronic component 30 electrically connected with the wiring layer 50; a first electrode 20 provided on the wiring layer 50 and electrically connected with the wiring layer 50; a metal joint material 22 provided on the first electrode 20; a second electrode 56 provided below the wiring layer 50 and protruding downward from the wiring layer; and an insulation part 40 where the electronic component 30, the first electrode 20, and the metal joint material 22 are embedded. When the electronic component built-in substrate 1 is laminated on another electronic component built-in substrate 1, the second electrode 56 is embedded in the metal joint material 22 to be joined thereto.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130711&DB=EPODOC&CC=JP&NR=2013138080A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130711&DB=EPODOC&CC=JP&NR=2013138080A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ISHIZUKI YOSHIKATSU</creatorcontrib><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE</title><description>PROBLEM TO BE SOLVED: To provide an electronic component built-in substrate having a new structure that deals with the thickness reduction when the electronic component built-in substrate is laminated.SOLUTION: An electronic component built-in substrate 1 includes: a wiring layer 50; an electronic component 30 electrically connected with the wiring layer 50; a first electrode 20 provided on the wiring layer 50 and electrically connected with the wiring layer 50; a metal joint material 22 provided on the first electrode 20; a second electrode 56 provided below the wiring layer 50 and protruding downward from the wiring layer; and an insulation part 40 where the electronic component 30, the first electrode 20, and the metal joint material 22 are embedded. When the electronic component built-in substrate 1 is laminated on another electronic component built-in substrate 1, the second electrode 56 is embedded in the metal joint material 22 to be joined thereto.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEOgjAQQFkcjPoPF2dJiiysRzmkhl6bch2cCDF1MkqCv-R_uvgBTG95722zL_WkJTg2GrSz3jGxQB1NL7lhGGI9SEChE1jk2KKWGAxfwJJ0rgHXwuoBcgM9WsMoxjHIzdPaeJ9tHtNzSYc_d9mxJdFdnub3mJZ5uqdX-oxXf1ZFWZSVqhSWq6Qf21tHaw</recordid><startdate>20130711</startdate><enddate>20130711</enddate><creator>ISHIZUKI YOSHIKATSU</creator><scope>EVB</scope></search><sort><creationdate>20130711</creationdate><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE</title><author>ISHIZUKI YOSHIKATSU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2013138080A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>ISHIZUKI YOSHIKATSU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ISHIZUKI YOSHIKATSU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE</title><date>2013-07-11</date><risdate>2013</risdate><abstract>PROBLEM TO BE SOLVED: To provide an electronic component built-in substrate having a new structure that deals with the thickness reduction when the electronic component built-in substrate is laminated.SOLUTION: An electronic component built-in substrate 1 includes: a wiring layer 50; an electronic component 30 electrically connected with the wiring layer 50; a first electrode 20 provided on the wiring layer 50 and electrically connected with the wiring layer 50; a metal joint material 22 provided on the first electrode 20; a second electrode 56 provided below the wiring layer 50 and protruding downward from the wiring layer; and an insulation part 40 where the electronic component 30, the first electrode 20, and the metal joint material 22 are embedded. When the electronic component built-in substrate 1 is laminated on another electronic component built-in substrate 1, the second electrode 56 is embedded in the metal joint material 22 to be joined thereto.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JP2013138080A |
| source | esp@cenet |
| subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
| title | ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, MANUFACTURING METHOD OF ELECTRONIC COMPONENT BUILT-IN SUBSTRATE, AND LAMINATION TYPE ELECTRONIC COMPONENT BUILT-IN SUBSTRATE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T02%3A55%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ISHIZUKI%20YOSHIKATSU&rft.date=2013-07-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2013138080A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |