SEMICONDUCTOR DEVICE AND SYSTEM

PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a cloc...

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Hauptverfasser:	IRITA TAKAHIRO, FUJIGAYA MASAKI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	IRITA TAKAHIRO FUJIGAYA MASAKI
description	PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a clock control circuit 9 which controls the clock generation circuit 10; and a notification signal generation circuit 11 which generates a notification signal NTC_SIG for performing the notification of a timing in which the clock control circuit 9 controls the clock generation circuit 10. A voltage to be supplied to the semiconductor device 1 is adjusted in response to the notification signal NTC_SIG generated by the notification signal generation circuit 11.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2013016105A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2013016105A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2013016105A3</originalsourceid><addsrcrecordid>eNrjZJAPdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRCI4MDnH15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGxgaGZoYGpo7GRCkCABvGIgc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND SYSTEM</title><source>esp@cenet</source><creator>IRITA TAKAHIRO ; FUJIGAYA MASAKI</creator><creatorcontrib>IRITA TAKAHIRO ; FUJIGAYA MASAKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a clock control circuit 9 which controls the clock generation circuit 10; and a notification signal generation circuit 11 which generates a notification signal NTC_SIG for performing the notification of a timing in which the clock control circuit 9 controls the clock generation circuit 10. A voltage to be supplied to the semiconductor device 1 is adjusted in response to the notification signal NTC_SIG generated by the notification signal generation circuit 11.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130124&DB=EPODOC&CC=JP&NR=2013016105A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130124&DB=EPODOC&CC=JP&NR=2013016105A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>IRITA TAKAHIRO</creatorcontrib><creatorcontrib>FUJIGAYA MASAKI</creatorcontrib><title>SEMICONDUCTOR DEVICE AND SYSTEM</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a clock control circuit 9 which controls the clock generation circuit 10; and a notification signal generation circuit 11 which generates a notification signal NTC_SIG for performing the notification of a timing in which the clock control circuit 9 controls the clock generation circuit 10. A voltage to be supplied to the semiconductor device 1 is adjusted in response to the notification signal NTC_SIG generated by the notification signal generation circuit 11.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAPdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRCI4MDnH15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGxgaGZoYGpo7GRCkCABvGIgc</recordid><startdate>20130124</startdate><enddate>20130124</enddate><creator>IRITA TAKAHIRO</creator><creator>FUJIGAYA MASAKI</creator><scope>EVB</scope></search><sort><creationdate>20130124</creationdate><title>SEMICONDUCTOR DEVICE AND SYSTEM</title><author>IRITA TAKAHIRO ; FUJIGAYA MASAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2013016105A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>IRITA TAKAHIRO</creatorcontrib><creatorcontrib>FUJIGAYA MASAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>IRITA TAKAHIRO</au><au>FUJIGAYA MASAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND SYSTEM</title><date>2013-01-24</date><risdate>2013</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a clock control circuit 9 which controls the clock generation circuit 10; and a notification signal generation circuit 11 which generates a notification signal NTC_SIG for performing the notification of a timing in which the clock control circuit 9 controls the clock generation circuit 10. A voltage to be supplied to the semiconductor device 1 is adjusted in response to the notification signal NTC_SIG generated by the notification signal generation circuit 11.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	SEMICONDUCTOR DEVICE AND SYSTEM
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T22%3A23%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=IRITA%20TAKAHIRO&rft.date=2013-01-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2013016105A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true