SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that suppresses characteristic degradation of an input main signal while reducing an inspection cost of jitter tolerance inspection.SOLUTION: A semiconductor integrated circuit 101 having the function of generating an inspection sig...
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| creator | KISHIMOTO SATOSHI KANEMITSU TOMOHIKO |
| description | PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that suppresses characteristic degradation of an input main signal while reducing an inspection cost of jitter tolerance inspection.SOLUTION: A semiconductor integrated circuit 101 having the function of generating an inspection signal in which a jitter signal is added to a main signal includes: a jitter signal generation section 50 for generating a signal on which the jitter signal is based; a buffer circuit 10 interposed between a power line Vcc and a ground line GND and powered by the power line Vcc to amplify and output the external main signal; and a jitter signal addition section 30 interposed between the power line Vcc and the buffer circuit 10 and between the buffer circuit 10 and the ground line GND to add the jitter signal to the main signal by varying the supply power from the power line Vcc to the buffer circuit 10 on the basis of the magnitude of the signal on which the jitter signal is based. |
| format | Patent |
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a buffer circuit 10 interposed between a power line Vcc and a ground line GND and powered by the power line Vcc to amplify and output the external main signal; and a jitter signal addition section 30 interposed between the power line Vcc and the buffer circuit 10 and between the buffer circuit 10 and the ground line GND to add the jitter signal to the main signal by varying the supply power from the power line Vcc to the buffer circuit 10 on the basis of the magnitude of the signal on which the jitter signal is based.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121210&DB=EPODOC&CC=JP&NR=2012244528A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121210&DB=EPODOC&CC=JP&NR=2012244528A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KISHIMOTO SATOSHI</creatorcontrib><creatorcontrib>KANEMITSU TOMOHIKO</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that suppresses characteristic degradation of an input main signal while reducing an inspection cost of jitter tolerance inspection.SOLUTION: A semiconductor integrated circuit 101 having the function of generating an inspection signal in which a jitter signal is added to a main signal includes: a jitter signal generation section 50 for generating a signal on which the jitter signal is based; a buffer circuit 10 interposed between a power line Vcc and a ground line GND and powered by the power line Vcc to amplify and output the external main signal; and a jitter signal addition section 30 interposed between the power line Vcc and the buffer circuit 10 and between the buffer circuit 10 and the ground line GND to add the jitter signal to the main signal by varying the supply power from the power line Vcc to the buffer circuit 10 on the basis of the magnitude of the signal on which the jitter signal is based.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgKdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFw9HNR8HUN8fB3UfB3AyoIDnB1DvH0c1cgpJOHgTUtMac4lRdKczMoubmGOHvophbkx6cWFyQmp-allsR7BRgZGBoZmZiYGlk4GhOlCADtvTKg</recordid><startdate>20121210</startdate><enddate>20121210</enddate><creator>KISHIMOTO SATOSHI</creator><creator>KANEMITSU TOMOHIKO</creator><scope>EVB</scope></search><sort><creationdate>20121210</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>KISHIMOTO SATOSHI ; KANEMITSU TOMOHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2012244528A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>KISHIMOTO SATOSHI</creatorcontrib><creatorcontrib>KANEMITSU TOMOHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KISHIMOTO SATOSHI</au><au>KANEMITSU TOMOHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2012-12-10</date><risdate>2012</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that suppresses characteristic degradation of an input main signal while reducing an inspection cost of jitter tolerance inspection.SOLUTION: A semiconductor integrated circuit 101 having the function of generating an inspection signal in which a jitter signal is added to a main signal includes: a jitter signal generation section 50 for generating a signal on which the jitter signal is based; a buffer circuit 10 interposed between a power line Vcc and a ground line GND and powered by the power line Vcc to amplify and output the external main signal; and a jitter signal addition section 30 interposed between the power line Vcc and the buffer circuit 10 and between the buffer circuit 10 and the ground line GND to add the jitter signal to the main signal by varying the supply power from the power line Vcc to the buffer circuit 10 on the basis of the magnitude of the signal on which the jitter signal is based.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING |
| title | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT |
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