MOS TYPE SEMICONDUCTOR DEVICE

MOS TYPE SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide an MOS type semiconductor device which does not cause any drop in breakdown voltage or increase in on resistance while reducing the manufacturing cost.SOLUTION: The MOS type semiconductor device comprises a p base region 17 arranged selectively on the surface layer o...

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1. Verfasser: NIIMURA YASUSHI
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Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description PROBLEM TO BE SOLVED: To provide an MOS type semiconductor device which does not cause any drop in breakdown voltage or increase in on resistance while reducing the manufacturing cost.SOLUTION: The MOS type semiconductor device comprises a p base region 17 arranged selectively on the surface layer of an ndrift layer 1 and having a base in the shape of a curvature, an n-type first region 6 arranged selectively on the surface layer of the p base region 17, a gate electrode 8 covering the surface of the p base region 17 held between the surface of the n-type first region 6 and the surface of the ndrift layer 1 with a gate insulating film 9 interposed therebetween, and a metal electrode 13 coming into conductive contact with the surface of the n-type first region 6 and the surface of the p base region 17. Net doping concentration of the p base region 17 is in such a shape as having a plurality of well regions.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2012033809A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2012033809A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2012033809A3</originalsourceid><addsrcrecordid>eNrjZJD19Q9WCIkMcFUIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhkYGxsYWBpaOxkQpAgDbPSGQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MOS TYPE SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NIIMURA YASUSHI</creator><creatorcontrib>NIIMURA YASUSHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide an MOS type semiconductor device which does not cause any drop in breakdown voltage or increase in on resistance while reducing the manufacturing cost.SOLUTION: The MOS type semiconductor device comprises a p base region 17 arranged selectively on the surface layer of an ndrift layer 1 and having a base in the shape of a curvature, an n-type first region 6 arranged selectively on the surface layer of the p base region 17, a gate electrode 8 covering the surface of the p base region 17 held between the surface of the n-type first region 6 and the surface of the ndrift layer 1 with a gate insulating film 9 interposed therebetween, and a metal electrode 13 coming into conductive contact with the surface of the n-type first region 6 and the surface of the p base region 17. Net doping concentration of the p base region 17 is in such a shape as having a plurality of well regions.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120216&amp;DB=EPODOC&amp;CC=JP&amp;NR=2012033809A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120216&amp;DB=EPODOC&amp;CC=JP&amp;NR=2012033809A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NIIMURA YASUSHI</creatorcontrib><title>MOS TYPE SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide an MOS type semiconductor device which does not cause any drop in breakdown voltage or increase in on resistance while reducing the manufacturing cost.SOLUTION: The MOS type semiconductor device comprises a p base region 17 arranged selectively on the surface layer of an ndrift layer 1 and having a base in the shape of a curvature, an n-type first region 6 arranged selectively on the surface layer of the p base region 17, a gate electrode 8 covering the surface of the p base region 17 held between the surface of the n-type first region 6 and the surface of the ndrift layer 1 with a gate insulating film 9 interposed therebetween, and a metal electrode 13 coming into conductive contact with the surface of the n-type first region 6 and the surface of the p base region 17. Net doping concentration of the p base region 17 is in such a shape as having a plurality of well regions.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD19Q9WCIkMcFUIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhkYGxsYWBpaOxkQpAgDbPSGQ</recordid><startdate>20120216</startdate><enddate>20120216</enddate><creator>NIIMURA YASUSHI</creator><scope>EVB</scope></search><sort><creationdate>20120216</creationdate><title>MOS TYPE SEMICONDUCTOR DEVICE</title><author>NIIMURA YASUSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2012033809A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NIIMURA YASUSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NIIMURA YASUSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MOS TYPE SEMICONDUCTOR DEVICE</title><date>2012-02-16</date><risdate>2012</risdate><abstract>PROBLEM TO BE SOLVED: To provide an MOS type semiconductor device which does not cause any drop in breakdown voltage or increase in on resistance while reducing the manufacturing cost.SOLUTION: The MOS type semiconductor device comprises a p base region 17 arranged selectively on the surface layer of an ndrift layer 1 and having a base in the shape of a curvature, an n-type first region 6 arranged selectively on the surface layer of the p base region 17, a gate electrode 8 covering the surface of the p base region 17 held between the surface of the n-type first region 6 and the surface of the ndrift layer 1 with a gate insulating film 9 interposed therebetween, and a metal electrode 13 coming into conductive contact with the surface of the n-type first region 6 and the surface of the p base region 17. Net doping concentration of the p base region 17 is in such a shape as having a plurality of well regions.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MOS TYPE SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T10%3A13%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NIIMURA%20YASUSHI&rft.date=2012-02-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2012033809A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true