GATE SELECTION CIRCUIT OF LIQUID CRYSTAL PANEL, ACCUMULATING CAPACITY DRIVING CIRCUIT, DRIVING DEVICE, AND DRIVING METHOD
PROBLEM TO BE SOLVED: To decrease the scale of a circuit in the gate selection circuit of an active matrix liquid crystal panel. SOLUTION: A plurality of clock signals Ck1/Ck2/Ck3/Ck4 are generated by a clock generation circuit 110. A shift register is formed of a plurality of latch circuits LA1(LA1...
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| creator | KATSUSE HIROFUMI MATSUMOTO KAZUHIRO OKUNO TAKESHI |
| description | PROBLEM TO BE SOLVED: To decrease the scale of a circuit in the gate selection circuit of an active matrix liquid crystal panel. SOLUTION: A plurality of clock signals Ck1/Ck2/Ck3/Ck4 are generated by a clock generation circuit 110. A shift register is formed of a plurality of latch circuits LA1(LA11to LA1n) and holding information Gdata is shifted in synchronization with enable clock signals Enable1/Enable2. Then, in a switch circuit SW1(SW11to SW1m), the plurality of clock signals Ck1/Ck2/Ck3/Ck4 are sequentially output as gate selection signals Gate , Gate , Gate , Gate , ..., Gate in accordance with output signals Q1, Q3, ... of the latch circuits LA1(LA11to LA1n). COPYRIGHT: (C)2011,JPO&INPIT |
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SOLUTION: A plurality of clock signals Ck1/Ck2/Ck3/Ck4 are generated by a clock generation circuit 110. A shift register is formed of a plurality of latch circuits LA1(LA11to LA1n) and holding information Gdata is shifted in synchronization with enable clock signals Enable1/Enable2. Then, in a switch circuit SW1(SW11to SW1m), the plurality of clock signals Ck1/Ck2/Ck3/Ck4 are sequentially output as gate selection signals Gate , Gate , Gate , Gate , ..., Gate in accordance with output signals Q1, Q3, ... of the latch circuits LA1(LA11to LA1n). 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SOLUTION: A plurality of clock signals Ck1/Ck2/Ck3/Ck4 are generated by a clock generation circuit 110. A shift register is formed of a plurality of latch circuits LA1(LA11to LA1n) and holding information Gdata is shifted in synchronization with enable clock signals Enable1/Enable2. Then, in a switch circuit SW1(SW11to SW1m), the plurality of clock signals Ck1/Ck2/Ck3/Ck4 are sequentially output as gate selection signals Gate , Gate , Gate , Gate , ..., Gate in accordance with output signals Q1, Q3, ... of the latch circuits LA1(LA11to LA1n). COPYRIGHT: (C)2011,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY EDUCATION FREQUENCY-CHANGING NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS SEALS TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF |
| title | GATE SELECTION CIRCUIT OF LIQUID CRYSTAL PANEL, ACCUMULATING CAPACITY DRIVING CIRCUIT, DRIVING DEVICE, AND DRIVING METHOD |
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