DISPLAY CONTROLLER

PROBLEM TO BE SOLVED: To provide a display controller capable of appropriately controlling the ON/OFF timing of a liquid crystal display and a backlight when the output of a clock signal is stopped or resumed. SOLUTION: A first counter 220 and a second counter 221 count the clock of a 5 MHz clock si...

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description PROBLEM TO BE SOLVED: To provide a display controller capable of appropriately controlling the ON/OFF timing of a liquid crystal display and a backlight when the output of a clock signal is stopped or resumed. SOLUTION: A first counter 220 and a second counter 221 count the clock of a 5 MHz clock signal. A pulse determining part 22 makes a backlight ON/OFF instruction signal into a low level, when the value of the counter of the first counter 220 reaches a reference value for turning off the backlight, because a 2ms pulse signal is not outputted and makes a PLL drive and stop signal into the low level, when the value of the counter of the first counter 220 reaches a reference value for stopping a PLL. The pulse determining part 22 makes the PLL stop and drive signal into a high level, when the output of the 2ms pulse signal is resumed and the value of the counter of the second counter 221 reaches a reference value for starting a PLL operation and makes the backlight ON/OFF instruction signal into the high level, when the value of the counter of the second counter 221 reaches a reference value for turning on the backlight. COPYRIGHT: (C)2011,JPO&INPIT
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SOLUTION: A first counter 220 and a second counter 221 count the clock of a 5 MHz clock signal. A pulse determining part 22 makes a backlight ON/OFF instruction signal into a low level, when the value of the counter of the first counter 220 reaches a reference value for turning off the backlight, because a 2ms pulse signal is not outputted and makes a PLL drive and stop signal into the low level, when the value of the counter of the first counter 220 reaches a reference value for stopping a PLL. The pulse determining part 22 makes the PLL stop and drive signal into a high level, when the output of the 2ms pulse signal is resumed and the value of the counter of the second counter 221 reaches a reference value for starting a PLL operation and makes the backlight ON/OFF instruction signal into the high level, when the value of the counter of the second counter 221 reaches a reference value for turning on the backlight. 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SOLUTION: A first counter 220 and a second counter 221 count the clock of a 5 MHz clock signal. A pulse determining part 22 makes a backlight ON/OFF instruction signal into a low level, when the value of the counter of the first counter 220 reaches a reference value for turning off the backlight, because a 2ms pulse signal is not outputted and makes a PLL drive and stop signal into the low level, when the value of the counter of the first counter 220 reaches a reference value for stopping a PLL. The pulse determining part 22 makes the PLL stop and drive signal into a high level, when the output of the 2ms pulse signal is resumed and the value of the counter of the second counter 221 reaches a reference value for starting a PLL operation and makes the backlight ON/OFF instruction signal into the high level, when the value of the counter of the second counter 221 reaches a reference value for turning on the backlight. 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subjects ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING
DISPLAY
EDUCATION
FREQUENCY-CHANGING
NON-LINEAR OPTICS
OPTICAL ANALOGUE/DIGITAL CONVERTERS
OPTICAL LOGIC ELEMENTS
OPTICS
PHYSICS
SEALS
TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
title DISPLAY CONTROLLER
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